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August 2019

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TechNet <[log in to unmask]>
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Date:
Wed, 28 Aug 2019 08:49:32 -0500
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TechNet E-Mail Forum <[log in to unmask]>, Jack Olson <[log in to unmask]>
Subject:
Re: TYPE III vs TYPE V vias
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Jack Olson <[log in to unmask]>
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On Tue, 27 Aug 2019 16:33:55 -0700, Stephen Pierce <[log in to unmask]> wrote:

>Area array pad over a plated via (blind or through) is the most common reason
>
>On Tue, Aug 27, 2019 at 3:49 PM Jack Olson <[log in to unmask]> wrote:
>>
>> When are caps on filled vias required by an application?

1) ours is a via array in single pad for thermal reasons, but we need 100% assurance no solder will make a bump on the back side
2) that's what I thought Dave was thinking about, too. just making sure I didn't misunderstand...

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