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August 2019

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TechNet E-Mail Forum <[log in to unmask]>, Stephen Pierce <[log in to unmask]>, "[log in to unmask]" <[log in to unmask]>
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Wed, 28 Aug 2019 00:06:41 +0000
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TechNet E-Mail Forum <[log in to unmask]>, Tan Geok Ang <[log in to unmask]>
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Re: TYPE III vs TYPE V vias
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Tan Geok Ang <[log in to unmask]>
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Especially on fine pitch and/or large area array I/O, due to PCB routing challenges or needs

________________________________

From: Stephen Pierce <[log in to unmask]>
Date: 28 August 2019 at 7:35:56 AM SGT
To: [log in to unmask] <[log in to unmask]>
Subject: Re: [TN] TYPE III vs TYPE V vias

Area array pad over a plated via (blind or through) is the most common reason

On Tue, Aug 27, 2019 at 3:49 PM Jack Olson <[log in to unmask]> wrote:
>
> When are caps on filled vias required by an application?

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