A void that does *not* expose a conductor is a process indicator.
A void that does expose a conductor is a defect.

Areas that are to be coated/not coated is tricky for some to properly
define.
If a customer says that everything that is not called out to be
coating-free is an area that *must* be coated than they can say a void or a
no-coat spot out on the flat-unencumbered is a defect. Which it is not and
will only have you spending excessive time fixing. That slippery slope will
also lead to calling coating free edges a defect, or the underside of a
raised component, etc.
The more sensible way is to say all *conductive* surfaces shall be coated.

Lloyd Duso
General Manager
Diamond-MT
(814) 535-3505
www.Diamond-mt.com


On Wed, Jun 12, 2019 at 9:50 AM Wayne Thayer <[log in to unmask]> wrote:

> We're trying to work through IPC guidelines for conformal coat inspection.
>
> What is the difference between a "void", which is allowed (but a process
> indicator) if the void doesn't expose conductors, and a "no coat", where
> "areas" specified for conformal coat are not completely covered?
>
> We have some tough masking requirements. Not only are they intricate, but
> we don't have tolerance information on the drawings. Clearly need to
> straighten that out, but we still want to be able to agree with suppliers
> on "void" vs "no coat".
>
> Thanks!
>
> Wayne Thayer
>