be careful walk on the boarder line - etch conductor usually has  
trapezoid shape, the conductor capacity should be calculated as  
average width x height (according to my book), but spacing is the  
highest conductor width to adjacent conductor - usually at bottom.   
to simplify the design margin issue, better use next high clearance  
(like the 31 V), instead of 30 V if you operated at 30 V.
In addition, dielectric strength of glass/FR4 are rather high -  
agree, make sure you don't switch to low dielectric laminate to  
improve signal using same layout (over looked usually by  
newbies... ).  and sure anodic filament is not an issue (usually high  
voltage is not that much of issue based on my knowledge.  Laura  
Turbini might proven me wrong.
best of luck.
jk
On Jan 28, 2019, at 4:12 PM, Robert Kondner wrote:

> Scott,
>
>  Actually I was saying internal layers are MUCH BETTER from an  
> insulation standpoint. When I would check safety distances the  
> internal traces can be 7 mil to pass safety ground to live  
> circuits. Do you know if that is correct? Dielectric strength of  
> FR4 is quite high.
>
>  A single layer of Kapton tape is rated at 5KV though I think that  
> is kind of pushing it. It is just that air is a very poor insulator.
>
> Bob K
>
> -----Original Message-----
> From: TechNet <[log in to unmask]> On Behalf Of Decker, Scott Collins
> Sent: Monday, January 28, 2019 3:49 PM
> To: [log in to unmask]
> Subject: Re: [TN] [External] [TN] IPC2221 Electrical Conductor  
> Spacing Requirements
>
> Bob,
>    Yes, for the short answer. You are correct in that the internal  
> layers "should" be as good as the outer for spacing but that's  
> assuming the same voltage. Since I'm in Aerospace I tend to take  
> the higher values unless I'm really pressed for space and even  
> then, there is generally a conversation with the engineers on what  
> is expected and best. It's been a 50/50 win rate for the most  
> part... :-) Later...
>
> Scott Decker | Senior Engineer, PCB Design Services CID+ |  
> Electronic Systems Center COLLINS AEROSPACE
> 3445 S. 5th Street, Suite 170, Phoenix, AZ 85040 U.S.A.
> Tel: 602 308 5957  FAX: 602 243 2347
> [log in to unmask]  www.collinsaerospace.com
>
> CONFIDENTIALITY WARNING: This message may contain proprietary and/ 
> or privileged information of Collins Aerospace Systems and its  
> affiliated companies. If you are not the intended recipient please  
> 1) do not disclose, copy, distribute or use this message or its  
> contents, 2) advise the sender by return e-mail, and 3) delete all  
> copies (including all
> attachments) from your computer. Your cooperation is greatly  
> appreciated.
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner
> Sent: Monday, January 28, 2019 11:47 AM
> To: [log in to unmask]
> Subject: Re: [TN] [External] [TN] IPC2221 Electrical Conductor  
> Spacing Requirements
>
> Hi,
>
>  For internal layers I am under the impression that higher voltage  
> can be handled at the same distances as on external layers.
>
>  The assumption here is internal glass and epoxy is a much better  
> insulator than the air and solder mask on the external.
>
>  Yes / No? Any thoughts?
> Bob K.
>
> -----Original Message-----
> From: TechNet <[log in to unmask]> On Behalf Of Decker, Scott Collins
> Sent: Monday, January 28, 2019 12:34 PM
> To: [log in to unmask]
> Subject: Re: [TN] [External] [TN] IPC2221 Electrical Conductor  
> Spacing Requirements
>
> Steven,
>   I would go with the maximum 31-50V option. For starts, the  
> spacing for the 16-30 is pretty small, so unless you are working  
> with some really high density trace spacing, use the 31-50V value.  
> Understanding that this is for the B4 bare board external traces  
> with a Soldermask. Even if you are on internal layers, I would use  
> the higher value just to be safe. In my opinion, you are just  
> looking to make it more robust and reliable in the long run. If you  
> want cutting edge, maybe you push it, but over time, you might find  
> yourself wishing you didn't? :-) Since you didn't mention what  
> layers these lines were on or if you had Soldermask on the outside,  
> but if not I would for sure go with the larger voltage spacing  
> value. Hope that helps.
> Later...
>
> Scott Decker | Senior Engineer, PCB Design Services CID+ |  
> Electronic Systems Center COLLINS AEROSPACE
> 3445 S. 5th Street, Suite 170, Phoenix, AZ 85040 U.S.A.
> Tel: 602 308 5957  FAX: 602 243 2347
> [log in to unmask]  www.collinsaerospace.com
>
> CONFIDENTIALITY WARNING: This message may contain proprietary and/ 
> or privileged information of Collins Aerospace Systems and its  
> affiliated companies. If you are not the intended recipient please  
> 1) do not disclose, copy, distribute or use this message or its  
> contents, 2) advise the sender by return e-mail, and 3) delete all  
> copies (including all
> attachments) from your computer. Your cooperation is greatly  
> appreciated.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Steven Schell
> Sent: Monday, January 28, 2019 9:55 AM
> To: [log in to unmask]
> Subject: [External] [TN] IPC2221 Electrical Conductor Spacing  
> Requirements
>
> Hello  Technetters,
>
> I am trying to interpret the electrical clearance requirements in  
> the IPC2221A standard, under section 6.3.
> Table 6-1 lists minimum spacing requirements for various voltage  
> ranges between conductors.
> The table indicates that this is for AC or DC peaks.
> I am trying to interpret that last part.
> Our application has a tracking power supply that provides a  
> variable DC output voltage.  The average DC voltage is between 16  
> and 30V, but the peak instantaneous DC voltage exceeds 31V.
> In this case, should I be complying with the minimum spacing  
> requirements for 16-30V, or should I be complying with the minimum  
> spacing requirements for 31-50V.
>
> I guess I am not clear what the intent of the voltage thresholds is.
>
> Thank you for any help or insight.