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January 2019

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Subject:
From:
Douglas Pauls <[log in to unmask]>
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Date:
Tue, 15 Jan 2019 12:00:58 -0600
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Jack,
This has been debated quite a bit over the years.  How much of the surface
HAS to be coated and how big can a bare patch be before it is a defect?
And if you allow a bare spot of X by X dimension, why not 2X by 2X or 10X
by 10X.  Do you REALLY only have to coat the exposed metal?

In my opinion, leaving small spots of uncoated areas over solder mask, or
the surface/bodies of plastic parts is not a risk or reliability hazard.
Right now, J-sTD-001 does not really address bare spots, unless you
consider a bare spot a void.  In such cases, it is only a defect if it
exposes metal or violates minimum electrical clearance.

*Douglas Pauls *| Principal Materials and Process Engr | Advanced
Operations Engineering

*COLLINS AEROSPACE*

400 Collins Road NE, MS 108-101, Cedar Rapids, IA  52498  USA

*Tel:* +1 319 295 2109 | *Mobile: *+1 319 431 3773

[log in to unmask]


On Tue, Jan 15, 2019 at 11:25 AM Jack Olson <[log in to unmask]> wrote:

> Thank You.
> I would also be interested to know for inspection purposes - although it is
> common for the whole board to be coated (except for masked areas of
> course), should we only raise the red flag for exposed components and
> conductive areas? I realize that the coating PROCESS may make it easier to
> coat everything, but if there is a missed spot that is just bare board, is
> it a FAILURE? How do other people document this?
> (I'm new to this subject. Well, to be more accurate, I've been conformal
> coating for decades but never had detailed discussion about it until
> recently. Hoping to avoid complicated documentation)
>
> On Thu, Jan 10, 2019 at 3:36 PM Jack Olson <[log in to unmask]> wrote:
>
> > Is it more common to conformal coat unplated mounting holes?
> > or designate a clearance diameter on the assembly drawing?
> >
>

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