very smart move of IPC... stay away - one of those issues experience  
and training will do a lot of good instead of set rules (number of  
layers, adjacent embedded components all changes the stiffness of the  
pannel... in addition to the degree of cure of laminate,  
specifically, if low dielectric is used for example... IMHO).
jk
On Nov 19, 2018, at 11:11 AM, Frank Kimmey wrote:

> Jack,
> I think IPC has stayed away from this due to all the variables  
> involved.
> I think De-Panelizing almost has to be AABUS.
> Either put your requirements into an internal spec (given to all  
> Suppliers) or on the print.
> Reasoning for this is one board may not matter if mouse bit, scored  
> or routed while another may only be routable.
> My personal is all PCBs shall be routed.
> It costs a little more but always works (form, fit, function)
> Your pick.
> Good Luck,
> FNK
>
> Frank N Kimmey CID+
> Electrical Engineer PCB Design
>
> 1400 W Stanford Ranch Road, Rocklin, CA 95765-3701 USA
> T 916 625 1818 | M 916 833 9877
> [log in to unmask]
>
>
>
>
>
> -----Original Message-----
> From: TechNet <[log in to unmask]> On Behalf Of Jack Olson
> Sent: Monday, November 19, 2018 6:34 AM
> To: [log in to unmask]
> Subject: [TN] depanelization
>
>  *** EXTERNAL EMAIL, think before you click. ***
>
> Is there any IPC document that addresses the METHOD of depanelization?
> (we have an array of assemblies in pallet form with break-away tabs)
>
> I found the acceptability of the RESULT of depanelization in IPC- 
> A-610 10.2.8, but that does not address the risk of the method  
> (stress on components and solder joints,etc).