TECHNET Archives

November 2018

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
Frank Kimmey <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Frank Kimmey <[log in to unmask]>
Date:
Mon, 19 Nov 2018 16:11:21 +0000
Content-Type:
text/plain
Parts/Attachments:
text/plain (1 lines)
Jack,

I think IPC has stayed away from this due to all the variables involved.

I think De-Panelizing almost has to be AABUS.

Either put your requirements into an internal spec (given to all Suppliers) or on the print.

Reasoning for this is one board may not matter if mouse bit, scored or routed while another may only be routable.

My personal is all PCBs shall be routed.

It costs a little more but always works (form, fit, function)

Your pick.

Good Luck, 

FNK



Frank N Kimmey CID+

Electrical Engineer PCB Design



1400 W Stanford Ranch Road, Rocklin, CA 95765-3701 USA

T 916 625 1818 | M 916 833 9877

[log in to unmask] 







      



-----Original Message-----

From: TechNet <[log in to unmask]> On Behalf Of Jack Olson

Sent: Monday, November 19, 2018 6:34 AM

To: [log in to unmask]

Subject: [TN] depanelization



 *** EXTERNAL EMAIL, think before you click. ***



Is there any IPC document that addresses the METHOD of depanelization?

(we have an array of assemblies in pallet form with break-away tabs)



I found the acceptability of the RESULT of depanelization in IPC-A-610 10.2.8, but that does not address the risk of the method (stress on components and solder joints,etc).


ATOM RSS1 RSS2