And one more thing I cannot stress enough, as long as so many are talking about reflow profiles:
All too often I see my process engineers/technicians focusing on homing in on a "perfect" reflow profile, placing TCs all over the map, drilling into the solder joint to achieve that revered "intimacy" and get as close to the Holy Grail of perfect correlation of the oven settings to the perfect solder joints across the entire CCA, minimizing the thermal gradients across the entire board, etc., etc.
And they do this on a single scrap board which is run through the oven until the oven profile is "perfect". Then, knowing they have the perfect profile, they let Production know they can start processing those boards, and they go get a cup of the really good coffee, go outside and take a long, well-deserved break, knowing that they will never have a soldering problem with that particular assembly again. Perhaps 20 minutes later there is a long line of operators at their desk complaining of "cold" or "disturbed" or "grayish" looking solder joints. The engineer, shocked beyond belief, runs out and checks the profile settings on the oven monitor and they all check out correct. So he grabs the profiling board and runs it through the oven again, and the profile tracks his saved profile (which he wisely printed out from the Mole or whatever he used and printed a Mylar of). He places the Mylar print of his profile over the latest profile print and it does not deviate more than +- two degrees over the entire curve. Befuddled, he scratches his head, and tells the line leader to run another production board, just one, so they can take a look at it. She does, and lo and behold, Donder and Blitzen, the board comes out perfect. So the engineer assumes they must not have had the oven warmed up properly (stupid operators!) and tells them it should be OK now. And a little while later it happens again.
Why?
Because all too often the profile does not take into account oven loading and the effect it has on the oven profile. When creating a profile, you need to put at least two or three scrap "loads" in front of and behind the profiling board in the oven, to ensure your oven settings will provide a thermal spectrum that can reflow one assembly passing through the oven alone, as well as 10 assemblies traveling through the oven a couple feet apart from each other. For some ovens, the variance on the chamber temperatures is extremely drastic. For other ovens with better recovery times, the variation is not so extreme. But if your profile is just a tweak above the minimum temperatures needed for a good soak, a proper ramp, a good time above solidus (time in liquidus), and the proper cooldown rate, you are definitely going to see variation in wetting, in IMF thickness, and a whole host of other issues during full-blown production in that oven.
And if you are using OSP, God help you my friend.
Odin
-----Original Message-----
From: George Wenger [mailto:[log in to unmask]]
Sent: Thursday, September 06, 2018 9:21 AM
To: 'TechNet E-Mail Forum'; Stadem, Richard D
Subject: RE: [TN] R: [TN] Ni intermetallic thickness target
I agree Richard. The difference sounds like a solder wetting variation do to the pad and not the reflow process.
RIGHT ON RICHARD OSP over bare copper is just below Immersion Tin which is at the top of my list of least favorite finishes.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Stadem, Richard D
Sent: Thursday, September 06, 2018 9:56 AM
To: [log in to unmask]
Subject: Re: [TN] R: [TN] Ni intermetallic thickness target
Dave's Rant and what you have posted below are all too true. But one thing I know for sure; OSP over bare copper is next to immersion tin on the bottom of my list of favorite finishes. I was wondering if the variation in IMF could be caused by some pads having thicker OSP coverage, and thus blocking or interfering with the wetting of the solder onto the pad during reflow? Is there a way you could mechanically or chemically remove the OSP on a scrap PWB on only some of the pads for the DDR3 part, then print the paste as you normally would and reflow the board using your existing reflow profile, then have them microsection that and see if you get different/better results? This would eliminate the part plating as a causal factor, and possibly prove the OSP is at least a major contributor to the issue, and possibly exonerate your reflow profile, thus eliminating several factors as the issue. My suspicion stems from the fact that if OSP is not properly applied immediately some of the copper pads may have oxidized, leading to the variation in IMF amongst pads. The simple fact that pads right next to each other have major variation pretty much rules out the reflow parameters unless there is a correlation between pads with heavy copper connections or some other cause.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
Sent: Thursday, September 06, 2018 7:10 AM
To: [log in to unmask]
Subject: Re: [TN] R: [TN] Ni intermetallic thickness target
We infer that an IMC has formed by visual evidence, wetting and spreading.
In the case of bottom only terminations we seek evidence by other means. We can't see the contact angle or determine what forces created the spreading.
In this case a lab cross sectioned a DDR3 memory device. The lab observed continuous intermetalic on the individual pads but characterized the IMC layer as too thin and inconsistent from pad to pad. Where one pad exhibited 70uin of IMC the neighboring pad measured less than 10uin. I found very little discussion of this in white papers. But, I did find a nicely done DOE, Effects of reflow profile and thermal conditioning on intermetallic compound thickness for SnAgCu soldered joints. This paper contained data about the thickness of IMC formed at different temperatures and dwell times. To some extent irrelevant because the base was OSP copper.
However, the standard deviations in measured data on this experiment were much lower than the deviations the lab found at the DDR memory pads. Is a large variation a cause for concern. How thin is too thin? My first impressions of the report fell in line with Dave's Rant, that trying to establish a reflow profile to achieve some standard IMC thickness was a fool's errand. But, on reflection, variation from assignable causes is always the enemy.
On Wed, Sep 5, 2018 at 6:01 PM Bob Landman <[log in to unmask]>
wrote:
> Hi Rich,
>
> You mean K100LD, right?
>
>
> https://www.kester.com/products/product/k100ld-lead-free-silver-free-a
> lloy-bar-solder
>
> Bob
>
> -----Original Message-----
> From: TechNet <[log in to unmask]> On Behalf Of Stadem, Richard D
> Sent: Wednesday, September 05, 2018 3:26 PM
> To: [log in to unmask]
> Subject: Re: [TN] R: [TN] Ni intermetallic thickness target
>
> That is also true, but there is really good information out there
> regarding the fact that too thick of an IMC is worse than too thin.
> That is because of the brittle nature of the alloy you end up with;
> nickel, gold, palladium, tin, and with SAC305 you add silver and copper.
> Although the gold, palladium, and silver are very low percentages, the
> combination of these and a significant percentage of nickel with no
> lead can make for a very brittle IMF, especially if it is at the 100
> uinch or thicker levels. So in that case, perhaps 20 to 70 uinches may
> be quite ideal. I am trying to find the reports I saved in my
> bottomless stack of "important stuff".
> Also, the IMF formation is self-limiting, but it depends on the
> factors of time above solidus, temperature, component plating, solder alloy type, etc.
> These were all listed as having significant impact on the thickness
> along with even very small amounts of germanium and other dopants. So,
> for example, Kester KL100D has very different properties from SAC305,
> yet it is almost 100% tin. KL100D is very similar to Sn63.
> If there was a concern, then I would rather rely on actual reliability
> tests taken over time, rather than the average thickness variation of
> a bunch of microsections. It's very difficult to guess at exactly what
> thickness might be ideal, but reliability results prove that, assuming
> you know for sure what thickness you have with your samples. And
> remember, the IMF grows over time; it is never the same 3 months or two years later.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of SALA GABRIELE
> Sent: Wednesday, September 05, 2018 1:39 PM
> To: [log in to unmask]
> Subject: [TN] R: [TN] Ni intermetallic thickness target
>
> Keep in mind also the terminal finishing.....
> One reflow or two reflow ? etc
>
> Too early to fix a reliable IMC thickness ..... too many variables
> playing !!!
>
> GS
>
>
> -----Messaggio originale-----
> Da: TechNet [mailto:[log in to unmask]] Per conto di Guy Ramsey
> Inviato: mercoledì 5 settembre 2018 19:34
> A: [log in to unmask]
> Oggetto: Re: [TN] Ni intermetallic thickness target
>
> ENEPIG
>
> On Wed, Sep 5, 2018 at 1:17 PM Stadem, Richard D
> <[log in to unmask]
> >
> wrote:
>
> > What is the finish plating?
> >
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
> > Sent: Wednesday, September 05, 2018 11:59 AM
> > To: [log in to unmask]
> > Subject: [TN] Ni intermetallic thickness target
> >
> > Recently, I was reviewing a lab report. It concluded that the
> > manufacturer should increase the IMC thickness as a part of process
> changes . . .
> > It stated that, while there are no industry specifications for IMC
> > thickness it s generally accepted that for Pb-free assemblies the
> > IMC thickness should be in the 20 to 120 uin range. It seems to be
> > critical of a process that produces IMC between 10 and 70 uin on
> > pads across a single device.
> > Does anybody have reference papers or texts that would support this
> > target and process critique?
> >
>
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