Good point, Joyce. And while the flatpack will go through reflow, Graham will need to make sure the transistor can also, from a max. temperature standpoint.

-----Original Message-----
From: Yuan-chia Joyce Koo [mailto:[log in to unmask]] 
Sent: Thursday, August 30, 2018 2:02 PM
To: TechNet E-Mail Forum; Stadem, Richard D
Subject: Re: [TN] qualifying a heatsink attach process

Graham,
look like it is two step process: (1) mounting heat sink to your  
parts (2) mounting parts to PWB - X-ray might be able to inspect with  
step (1) effectively, but if you do the X-ray after assembly, it  
would be difficult - assume you use high power transistor, you have  
high power layout board with heavy metal layers.  The transistor/heat  
sink is relatively easy to inspect by X-ray (semi basically is  
transparent, you can see the voids at heat sink easily).  If you want  
to inspect at assembly level, you better have 3D X-ray and do the  
slice (even that the signal might not be that good if your board got  
heavy metal layout). preform at parts level is great - after reflow,  
you don't need to worry too much at assembly level for 2nd melt (not  
much flux)... but do it after the PWB process, silver epoxy (liquid)  
is much better with a proper weight.  IMHO.
Look like your customer did heat sink attachment as after thought -  
fix a immature design... just be careful (of course, designer is  
always right as long as they don't need to build it in masses).
good luck.
jk
On Aug 30, 2018, at 2:33 PM, Stadem, Richard D wrote:

> There are many labs that offer X-ray or CT scans, along with  
> microsectioning, etc. For a one-time or for occasional requirements  
> they are great.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Graham Collins
> Sent: Thursday, August 30, 2018 1:26 PM
> To: [log in to unmask]
> Subject: [TN] qualifying a heatsink attach process
>
> Hi technet!
>
> We've got a customer working with high power transistors, they want to
> use solder pre-forms to solder a heatsink on top of a row of
> transistors.  So the stackup will be PCB - transistor - preform -
> heatsink, where the heatsink will span a row of 5 transistors.
>
> The question is how do we establish that this is working OK and isn't
> full of voids?  This is at the "ok, we think this will work but we  
> need
> to qualify the attachment method" stage.  I've come up with a  
> couple of
> options:
>
> 1) tear / grind it off and look for anomalies - not very sure to find
> issues.
> 2) x-ray it - we don't have a 3-d x-ray so I'm not confident in our
> abilities to find voiding.  We do have a nice static x-ray though and
> will try it to see how well it can see.
> 3) Sonoscan it to look for voids?  Would have to be outsourced.
>
> Am I missing any obvious options?
>
> -- 
> Graham Collins
> Senior Process Engineer
> Sunsel Systems
> (902) 444-7867