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June 2018

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From:
"Stadem, Richard D" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Stadem, Richard D
Date:
Mon, 11 Jun 2018 17:00:21 +0000
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I agree with Bob, but wish to point out two items not considered. If you have 5 mil spacing between the scratched traces, and if in fact the scratches penetrated past the soldermask, even ever so slightely into the metal, there is ALWAYS some copper spread past the edge of the trace, and it is nearly always visible under 30x magnification or so.

If there is no metal glinting through the bottom of the scratch, then no chance of cut trace nor no chance of electrical clearance violation between the edge of the trace and any adjacent conductor.

Second, if the customer does not like the IPC specification, they are certainly free to impose their own criteria, but the groundrules state that any exceptions to the standards are documented in the documentation package, ie, the BOM, the PWB fabrication drawing, or the assembly drawing, or the contract.

If any exceptions are NOT noted, then the order of precedence falls back to the IPC documents. If any exceptions are made after the fact, that constitutes scope creep; the customer can accommodate the changes if properly documented, but must also be free to charge for any rework that may result of the change in conditions.

dean



-----Original Message-----

From: TechNet [mailto:[log in to unmask]] On Behalf Of Bob Wettermann

Sent: Monday, June 11, 2018 11:46 AM

To: [log in to unmask]

Subject: Re: [TN] 答复: Interpretation of IPC standard for Solder Mask Scratches on PCBA



Technically this is not a defect based on your description BUT you may have

to follow the golden rule-he who holds the gold makes all the rules.



The only possibility is that a form/fit/function is not satisfied due to

the existence of the scratches (would find that somewhat hard to believe

but there may be some issues if the reflection of light off of the PCB has

some impact on the circuit functioning properly).



I would suggest asking if repairs are allowed (If you can repair the mask

which is easy to do).



Also if you capitulate to their request I would make sure that the customer

spells out what the accept/reject criteria look like? How deep can the

scratches be? How long? Where?



If it's not in the spec and you are inspecting to the spec then the spec

needs to change.



Bob/BEST Inc



On Sun, Jun 10, 2018 at 8:06 PM, Willis Tam <[log in to unmask]> wrote:



> Hi All,

>

> Any comments and suggestion will be highly appreciated.

>

> B.R.

> WT

>

> -----邮件原件-----

> 发件人: TechNet [mailto:[log in to unmask]] 代表 Willis Tam

> 发送时间: 2018年6月5日 10:23

> 收件人: [log in to unmask]

> 主题: [TN] 答复: Interpretation of IPC standard for Solder Mask Scratches on

> PCBA

>

>

> Hi Technet,

>

>

> We have some arguments with one of our customers on the interpretation of

> IPC standard for Solder Mask Scratches on PCBA.

>

> According to IPC-A-610F §10.7.2. Solder Mask Coating-Voids, Blisters,

> Scratches.

> Acceptable- Class 1,2,3.

> Blister, Scratches, Voids that do not expose conductors and do not bridge

> adjacent conductors, conductor surface or create a hazardous condition

> which would allow loose mask particles to become enmeshed in moving parts

> or lodged between two electronically conductive mating surfaces.

>

>

> Customer's product specification defined the PCBA to be compliance to

> IPC-A-610F standard Glass 3.

> Customer found some scratches on solder mask surface on some of the

> PCBAs,  the scratches are minor scratches, not deep/heavy scratches, not

> expose conductors(copper traces under solder mask), but go across the

> adjacent conductors;

> We considered those scratches acceptable according to IPC-A-610F §10.7.2,

> but customer said not acceptable.

>

> The main argument is: customer considered any scratch which go across

> adjacent conductors as rejection, (Bridge adjacent conductors = go across),

> even not expose conductor.

> This is an 5mil/5mil(width/space) board, not accept scratches which go

> across adjacent conductors means not accept scratch of 10mil (0.25mm)

> length.

>

> I would like to seek clarification from IPC guru so that we move forward

>

>

> Best Regards

> Willis Tam

>

>

>

>

>





-- 

Bob Wettermann

BEST Inc

[log in to unmask]

Cell: 847-767-5745


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