Hi All,



Any comments and suggestion will be highly appreciated.



B.R.

WT



-----邮件原件-----

发件人: TechNet [mailto:[log in to unmask]] 代表 Willis Tam

发送时间: 2018年6月5日 10:23

收件人: [log in to unmask]

主题: [TN] 答复: Interpretation of IPC standard for Solder Mask Scratches on PCBA





Hi Technet,





We have some arguments with one of our customers on the interpretation of IPC standard for Solder Mask Scratches on PCBA.



According to IPC-A-610F §10.7.2. Solder Mask Coating-Voids, Blisters, Scratches.

Acceptable- Class 1,2,3.

Blister, Scratches, Voids that do not expose conductors and do not bridge adjacent conductors, conductor surface or create a hazardous condition which would allow loose mask particles to become enmeshed in moving parts or lodged between two electronically conductive mating surfaces.





Customer's product specification defined the PCBA to be compliance to IPC-A-610F standard Glass 3.

Customer found some scratches on solder mask surface on some of the PCBAs,  the scratches are minor scratches, not deep/heavy scratches, not expose conductors(copper traces under solder mask), but go across the adjacent conductors;

We considered those scratches acceptable according to IPC-A-610F §10.7.2, but customer said not acceptable.



The main argument is: customer considered any scratch which go across adjacent conductors as rejection, (Bridge adjacent conductors = go across), even not expose conductor.

This is an 5mil/5mil(width/space) board, not accept scratches which go across adjacent conductors means not accept scratch of 10mil (0.25mm) length.



I would like to seek clarification from IPC guru so that we move forward





Best Regards

Willis Tam