At the risk of repeating myself, go in search of as-is board or boards and do an analysis to see if related PTH precursors or latent defects are in evidence.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jose A Rios
Sent: Thursday, April 19, 2018 2:51 PM
To: [log in to unmask]
Subject: Re: [TN] [TN] R: [TN] PCB failure
There are so many contributors to IPSep, that troubleshooting can be very broad, and at the same time elusive. Given one image, many can suggest widely different failure mechanisms based on previous experiences (many of us were consumed by this in the 90’s, while implementing our own fixes). At the same time, I would not rule out hand-soldering as a contributor.
Have you qualified your hand-soldering operation across a range of assembly process conditions and board designs (and devices as applicable)? If not, it may be difficult to adjudicate this to fab alone. The same way the board is new to fab, it could also be ‘new’ to assembly as well. The thermal stress method your supplier used during lot conformance (IPC-TM-650 2.6.8), may not be an exact match to your hand-soldering process.
Agree with others here that you’ll need to evaluate PTH's before and after hand-soldering (at least for benchmarking purposes) so you know the structural integrity of the board(s) as received.
The presence of laminate cracks near the rim of the PTH (within the thermal zone) is not a reason for rejection on thermally stressed lot acceptance samples. Also, laminate materials, wet processes and methods of fab have evolved such that IPSep (as shown in the image) should be less prevalent now.
José (Joey) Ríos, Sr QA Engineer
Mission Assurance Manager
Kavli Institute for Astrophysics & Space Research Massachusetts Institute of Technology [log in to unmask]<mailto:[log in to unmask]>
(617)324-6272
On Apr 19, 2018, at 3:55 PM, Zilber Gil <[log in to unmask]<mailto:[log in to unmask]>> wrote:
Thanks,
I will dig into it next week. I will probably have an unpleasant discussion with the PCB fab :(
Regards,
Gil
נשלח מסמארטפון ה-Samsung Galaxy שלי.
-------- הודעה מקורית --------
מאת: Dwight Mattix <[log in to unmask]<mailto:[log in to unmask]>>
תאריך: 19.4.2018 19:39 (GMT+01:00)
אל: [log in to unmask]<mailto:[log in to unmask]>
נושא: Re: [TN] R: [TN] R: [TN] PCB failure
Holy Post-Sep Batman!
Concur, that's not assembly heat. Well yeah it likely is but an afternoon in the sun on the dashboard of your car might have been enough heat to pull that interconnect apart.
IMAO (in my arrogant opinion), that's just a poorly fab'd PTH.
For starters Sherlock Holmes:
1. Does the supplier have sections from this lot (both inprocess plating and final Met lab QC and solder float eval)? Review those 2.Do you or the supplier have any "as-is" boards that have not as yet been through reflow?
If yes, get busy sectioning those and look for precursors. Go crazy and do some vertical grinds down to look at the post interconnect in the horizontal. I'll lay you odds you'll see dark rings and/or gaps at the hole/foil plating interface.
Be prepared to go deeper into process logs, looking at actual working travelers, and chem lab info. They either had a recipe they dropped the ball on, or they don't have a recipe that's worth the paper it's written on. (once again, that's IMAO)>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey
Sent: Thursday, April 19, 2018 10:20 AM
To: [log in to unmask]<mailto:[log in to unmask]>
Subject: Re: [TN] R: [TN] R: [TN] PCB failure
I would like to see an image of the full via, top to bottom. But, I see no evidence that the failure was caused by excessive heat from hand soldering.. Obviously, they failure could be heat induced, but the board structures show no signs of heat stress. They didn't put up much of a fight from what is visible in the photo.
On Thu, Apr 19, 2018 at 12:49 PM, Zilber Gil <[log in to unmask]<mailto:[log in to unmask]>> wrote:
We require 0-5 micron etch back.
Gave the explanation previously.
Regards,
Gil
נשלח מסמארטפון ה-Samsung Galaxy שלי.
-------- הודעה מקורית --------
מאת: David Hillman <[log in to unmask]<mailto:[log in to unmask]>>
תאריך: 19.4.2018 16:43 (GMT+01:00)
אל: [log in to unmask]<mailto:[log in to unmask]>
נושא: Re: [TN] R: [TN] R: [TN] PCB failure
Hi Wayne - etchback isn't necessary for acceptable PTH reliability for some products and product use environments so that may not be a contributing issue. With that being said, I like etchback as it always makes the inner connections better/more robust and in some product use environments having etchback is necessary for long term product life.
One question we haven't asked as a group is " was etchback required in the fabrication requirements?"
Dave
On Thu, Apr 19, 2018 at 9:11 AM, Wayne Showers < [log in to unmask]<mailto:[log in to unmask]>
wrote:
The real problem is that this PCB has no etchback, positive or negative (PCBs are defective). As far as resin recession, yes the processing probably caused the separation, but once again, the PCB has no etchback.
I would send that cross-section image to the PCB supplier and asked them if this is typical. I suspect that they will realize it is a trap and either offer a crazy answer or admit that their is no etchback and offer to re-run/replace the PCBs.
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