TECHNET Archives

March 2018

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
"Stadem, Richard D" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Stadem, Richard D
Date:
Mon, 5 Mar 2018 14:04:08 +0000
Content-Type:
text/plain
Parts/Attachments:
text/plain (1 lines)
I am not prepared to provide input on what is an acceptable void size limit as a percentage of the overall solder connection between part and pad. Perhaps this should be with respect to the total overall wetted area in any given X-ray (perhaps a lesser maximum diameter as a percentage of the total pad area if the wetted area cannot be distinguished from the pad area). If a "better" X-ray is used that CAN distinguish the wetted area from the pad area, then perhaps a slightly larger maximum diameter as a percentage of the visible wetted area could be used.



As Dave noted, there can be very specific requirements between different parts as to the amount of voiding that is acceptable for both electrical and heatsinking requirements for some components as opposed to others, and trying to come up with criteria that will work for at least 90% of the parts out there without adding a huge cost may not be possible. I am guessing that we can come up with some guidelines, but would also have to provide a caveat; "except as required by the component manufacturer or AABUS".



But I would like to have the words "Note! A complete lack of voids as seen in an X-ray of a BTC does not necessarily mean perfect wetting between the bottom of the component and the pad(s) on the board. Insufficient solder paste height can leave a well-wetted board termination pad, with no connection whatsoever to the bottom of the part. This will show up in the X-ray as a "void-free" solder connection."



I have seen this too many times (even from experienced engineers) who are attempting to optimize the amount of solder paste deposited to reduce voiding. The peripheral solder connections hold the part up, the solder paste wets out on the belly pad on the board, but no connection is made between the belly pad on the bottom of the part and the belly pad on the PWB, only the peripheral connections have a finished solder joint. The X-ray is opaque and void free and the part works perfectly during short-term electrical test, but then fails prematurely because no required heatsinking is taking place.



-----Original Message-----

From: TechNet [mailto:[log in to unmask]] On Behalf Of David Hillman

Sent: Saturday, March 03, 2018 6:54 PM

To: [log in to unmask]

Subject: Re: [TN] Bottom Termination Components (BTC) Voiding Limits



Hi Wayne - you have good timing with your question as I can give you the latest info from the IPC committee meeting last week. The JSTD-001 committee had a comment submitted asking for void criteria for BTCs.  A small task group with global representation from several industry product segments was formed to review the issue. We reviewed the issue with data resources from consortia, IPC and SMTA resources.  We had one very specific

conclusion: Any void criteria that would be put into the JSTD-001 specification would be addressing solder joint integrity only. Many BTCs have either thermal or electrical functional needs which is a design issue that should be addressed during the product design phase.  Here is what the task team responded back to the JSTD-001 committee with:



"The JSTD-001 QFN Void Criteria task group recommends that a "request for data" be issued as a review of the current available industry data was found to not be sufficient to establish a data based maximum void criteria for solder joint integrity. The voiding criteria requirements pertaining to the functionality of a QFN or other Bottom Terminated Components (i.e.

thermal or electrical performance) are a design function and not part of the IPC-JSTD-001 specification scope. The "request for data" responses should be sent to the QFN Void Criteria task group by October 31st, 2018 so that they can be reviewed prior to the 2019 IPC JSTD 001 APEX committee meeting. The  JSTD-001 QFN Void Criteria task group will provide a void criteria recommendation to the IPC JSTD 001 committee based on the data submissions at the  2019 IPC JSTD 001 committee meeting."



The void number you listed - especially the 25% - have little to no technical data justification in terms of solder joint integrity.The

JSTD-001 BTC Void task group is looking for DOE/test/investigation data and there will be a recommendation to the JSTD-001 committee for review at the

2019 committee APEX meeting. I understand that seems like a long time but any criterial that is put into the JSTD-001 specification must be done based on data as those requirements results in costs to the industry.



A number of OEMs verbally committed to providing BTC void data to the

JSTD-001 BTC Void task group so I am confident the issue will be resolved within the year. If anyone has  data they would like  to submit to the task group, please send it to me and I'll make sure it is included in the data review.



Let me know if you have any additional questions.





Dave Hillman

IPC JSTD-001 BTC task group lead

Rockwell Collins

[log in to unmask]





On Sat, Mar 3, 2018 at 6:18 PM, Wayne Showers <[log in to unmask]>

wrote:



> I do not know of an IPC criteria on this.  I have seen 25% (The BGA

> criteria) cited, but this is not, to my knowledge accurate.

> The limits I have used in the past are 50% Coverage with no void 

> exceeding 15% in the center and no more than 10% anywhere else.

> I also used a 70% Coverage and 10% Void criteria for a very heat 

> sensitive application.

>

> Question 1: Is there now a citable IPC criteria? and if NO, Question 

> 2: What are some of this groups recommended criteria?

>

> Thanks and Regards, Wayne Showers, NPI/Technical Manager, 4Front 

> Solutions

>


ATOM RSS1 RSS2