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Subject:
From:
Yuan-chia Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Yuan-chia Joyce Koo <[log in to unmask]>
Date:
Thu, 22 Mar 2018 14:38:55 -0400
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text/plain (41 lines)
typo "SPGA" should be FPGA... sorry.
On Mar 22, 2018, at 2:36 PM, Yuan-chia Joyce Koo wrote:

> besides ITRS outlined roadmap pin  counts (which all industry tend  
> to bench mark and try to keep in line), there is a diminish of  
> return when you goes to too high pin counts - not only causes  
> layout problem, but also production yield issues - e.g. >1000  
> interconnect better  have very flat on both components and PWB...  
> you might need to go for LGA instead of BGA... as for prototype,  
> those components are killers to testing initial functionality of  
> the system (too complex).  rather than block set of components  
> instead - that is why initial customer chip is SPGA, until the  
> funcationality are defined to set into ASIC to speed things up and  
> save the real estate... (more integrate on chip the better -  
> anything walk off chip is a problem... impedance, fan out,  
> etc.etc.  you want as  simple  as  possible - as lower pin count   
> as possibly, not more... IMHO...  if  you give designer max  pin  
> count can be achieved for I/O, I bet he/she will used to max  
> +10%...  leave you little or no room but many headache to try to  
> layout on PWB... )... By the way, you didn't  say what PWB tech you  
> intende to use - 4/4? or 3/3? without knowing that, it is missing  
> half of the selection criteria... IMHO.  One more thing, assume you  
> have deep pocket - e.g. you can custom make high density ACF if you  
> have enough volume or intend to use next gen pin count outlined in   
> ITRS...  (although ITRS is no longer publish roadmap, I believe it  
> old version still cover next few years).
> my 1.4 cents.
> jk
> On Mar 22, 2018, at 12:07 PM, Ahmad, Syed wrote:
>
>> We are trying to determine limits on solder or other interconnects  
>> for a high pin count prototype and need help in identifying  
>> suppliers for solders, stencil manufacturers, ACAs, ACFs and other  
>> options that may help us achieve lowest pitch interconnects. All  
>> help is welcome. Thank you for your assistance. Suppliers may  
>> contact me directly on my email.
>>
>> Syed Sajid Ahmad,
>> Research Staff, ECE, NDSU
>> Cell 701-200-1674

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