Hi folks - I very much appreciate the response so far but I do want to
clarify the IPC BTC Void task team request: we are looking for solder joint
reliability data demonstrating the impact of voids on the solder joint
integrity of the BTC component. There are a large number of investigations
on how to reduce or eliminate BTC voids but the task team is specifically
looking for solder joint integrity based on thermal cycle or vibration or
drop shock etc.  Any data you can send me on void reduction/elimination I
would make sure the  IPC-7093 committee reviews so that is wonderful
information to receive too. If you email me the studies/investigations, I
will make sure it gets to the right place.

Dave Hillman
JSTD-001 BTC Void task team lead
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On Mon, Mar 5, 2018 at 3:51 PM, Wayne Showers <[log in to unmask]>
wrote:

> Dave et al,
> You can add me to the list of companies that will provide voiding data.  I
> am data mining variations of the print pattern to reduce voiding and I am
> in the process of marrying up stencil design to void and fill percentages.
>
> I can echo the voiding request from Blackberry.  The original request was
> 90% coverage and no more than 3 voids with no single void greater than 5%.
> Even to get to the 70%, I ended up using a custom solder slug and still had
> voiding due to via in pad.
>
> I would like to see a standard that reflects something similar to the
> following:
> Class 1: Undefined
> Class 2: Shall be 50% coverage with no single void exceeding X% or as
> defined by customer or part manufacturer.
> Class 3: Shall be 70% coverage with no single void exceeding X% or as
> defined by customer or part manufacturer.
> Note 1: Customer Requirements supersede
> Note 2: Manufacturer Recommendations/Requirements supersede
> Note 3: VIA in Pad and other design factors shall be considered and
> evaluated if criteria cannot be met.
>