not exact number %. the amp split ground is a killer - you need to
keep % low for voiding... (not 5%, but in the teen)... make sure the
voids is not concentrated on one corner that effect with few non-
wetting vias in the ground... as for the lead, you need enough
solder, but not too much, otherwise, you can have negative angle
(end lead with droplet shape joints), it impact cycling life (crack
initiation site right at interface... it also depend upon the package
leads style. lead frame cut off (Cu extended to the side of the
package after singulation), is more sensitive to negative solder
contact angle...
good luck dave.
jk
On Mar 5, 2018, at 3:21 PM, BEV CHRISTIAN wrote:
> TechNetters,
> I bet that the % voiding under the thermal pad of a BTC could be
> 80% and still be good for the “solder joint integrity” of THAT
> PARTICULAR SOLDER JOINT. Dave mentions that the committee is only
> gong to comment on the solder joint integrity, nothing else. But
> of course the ridiculous % amount of voiding I mention would cause
> havoc with the signal peripheral joints, as I think Joyce and maybe
> one or two others have already mentioned. Now the designers at
> BlackBerry were always asking for, get this, 5% voiding (or less).
> We told them if it happened it would be by chance, we could not
> guarantee it. What we did agree to was a certain percentage
> voiding under the IC in the package. I’m sorry I cannot recall
> what that % was. Joyce, do you remember? I think thermal modelling
> for the particular part, current and board design are going to be key.
>
> Regards,
> Bev
>
> Sent from Mail for Windows 10
>
> From: David Hillman
> Sent: Monday, March 5, 2018 2:50 PM
> To: [log in to unmask]
> Subject: Re: [TN] Bottom Termination Components (BTC) Voiding Limits
>
> Hi Gabriele - the IPC BTC Voids task group is coordinating with the
> IPC-7093 specification committee so that both specifications are in
> sync.
> Just as the JSTD-001 has the BGA void requirements and the IPC-7095
> specification contains the BGA void design aspect/assessment
> guidance, the
> JSTD-001 and the IPC-7093 specification will have a similar
> relationship
> for BTC voiding.
>
> Dave
>
> On Mon, Mar 5, 2018 at 11:26 AM, SALA GABRIELE <[log in to unmask]>
> wrote:
>
>> Many Thanks Dave,
>>
>> are the BTC Task Group (5-21h ? ) doing same void limits
>> assessment for
>> the coming IPC-7093 A Review ?
>>
>> Best Regards
>> Gabriele
>>
>> -----Messaggio originale-----
>> Da: TechNet [mailto:[log in to unmask]] Per conto di David Hillman
>> Inviato: domenica 4 marzo 2018 01:54
>> A: [log in to unmask]
>> Oggetto: Re: [TN] Bottom Termination Components (BTC) Voiding Limits
>>
>> Hi Wayne - you have good timing with your question as I can give
>> you the
>> latest info from the IPC committee meeting last week. The JSTD-001
>> committee had a comment submitted asking for void criteria for
>> BTCs. A
>> small task group with global representation from several industry
>> product
>> segments was formed to review the issue. We reviewed the issue
>> with data
>> resources from consortia, IPC and SMTA resources. We had one very
>> specific
>> conclusion: Any void criteria that would be put into the JSTD-001
>> specification would be addressing solder joint integrity only.
>> Many BTCs
>> have either thermal or electrical functional needs which is a
>> design issue
>> that should be addressed during the product design phase. Here is
>> what the
>> task team responded back to the JSTD-001 committee with:
>>
>> "The JSTD-001 QFN Void Criteria task group recommends that a
>> "request for
>> data" be issued as a review of the current available industry data
>> was
>> found to not be sufficient to establish a data based maximum void
>> criteria
>> for solder joint integrity. The voiding criteria requirements
>> pertaining to
>> the functionality of a QFN or other Bottom Terminated Components
>> (i.e.
>> thermal or electrical performance) are a design function and not
>> part of
>> the IPC-JSTD-001 specification scope. The "request for data"
>> responses
>> should be sent to the QFN Void Criteria task group by October
>> 31st, 2018 so
>> that they can be reviewed prior to the 2019 IPC JSTD 001 APEX
>> committee
>> meeting. The JSTD-001 QFN Void Criteria task group will provide a
>> void
>> criteria recommendation to the IPC JSTD 001 committee based on the
>> data
>> submissions at the 2019 IPC JSTD 001 committee meeting."
>>
>> The void number you listed - especially the 25% - have little to no
>> technical data justification in terms of solder joint integrity.The
>> JSTD-001 BTC Void task group is looking for DOE/test/investigation
>> data
>> and there will be a recommendation to the JSTD-001 committee for
>> review at
>> the
>> 2019 committee APEX meeting. I understand that seems like a long
>> time but
>> any criterial that is put into the JSTD-001 specification must be
>> done
>> based on data as those requirements results in costs to the industry.
>>
>> A number of OEMs verbally committed to providing BTC void data to the
>> JSTD-001 BTC Void task group so I am confident the issue will be
>> resolved
>> within the year. If anyone has data they would like to submit to
>> the task
>> group, please send it to me and I'll make sure it is included in
>> the data
>> review.
>>
>> Let me know if you have any additional questions.
>>
>>
>> Dave Hillman
>> IPC JSTD-001 BTC task group lead
>> Rockwell Collins
>> [log in to unmask]
>>
>>
>> On Sat, Mar 3, 2018 at 6:18 PM, Wayne Showers <
>> [log in to unmask]>
>> wrote:
>>
>>> I do not know of an IPC criteria on this. I have seen 25% (The BGA
>>> criteria) cited, but this is not, to my knowledge accurate.
>>> The limits I have used in the past are 50% Coverage with no void
>>> exceeding 15% in the center and no more than 10% anywhere else.
>>> I also used a 70% Coverage and 10% Void criteria for a very heat
>>> sensitive application.
>>>
>>> Question 1: Is there now a citable IPC criteria? and if NO, Question
>>> 2: What are some of this groups recommended criteria?
>>>
>>> Thanks and Regards, Wayne Showers, NPI/Technical Manager, 4Front
>>> Solutions
>>>
>>
>>
>> ---
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>>
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