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Subject:
From:
Yuan-chia Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Yuan-chia Joyce Koo <[log in to unmask]>
Date:
Wed, 28 Mar 2018 16:31:25 -0400
Content-Type:
text/plain
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text/plain (88 lines)
agree 2 or 3 time rework max.  it covered in the qual: 2x top 1x  
bottom plus 1x selective reflow plus 2 rework (including some times  
the last on most expansive  parts as local reflow e.g. processor) -  
provide your board solderability and dielectric plus warpage can  
handle 5 - 6 reflow (you specified the time duration of each Tp ) and  
qual 100% of your units or at least 50% of your units using those  
special made unit to prove worst case reliability (personally, like  
50% reworked and 50% std, so you can  see two group difference... if  
not mess up your spc chart and MTBF value).  IMHO.
if you have few expansive parts and your other stuff is the one needs  
rework, you design board to be testable prior to the pricy parts  
on... and populate them after to minimize the heat effect (some MEMS,  
optical, or high density MCM or ASIC).  you need work with design.
jk

On Mar 28, 2018, at 2:03 PM, Bhanu Sood wrote:

> Rework or scrap? the risk is usually assessed by weighing in the  
> laminate
> type (PI, FR-4, flex etc), design, board stack-up, components in  
> vicinity
> of rework site and time/temperature required for each rework  
> (including
> preheat).
>
>
> Any guidelines regarding the number of allowable reworks are going  
> to be
> specific to a design/material combination, tricky to extrapolate that
> guidance into a standard…rework risk assessment needs to analyze all
> factors and be better understood with solid research.  Most  
> companies say a
> site can be reworked 2 or 3 times (assuming high Td/Tg PI...$$$).
>
>
>
> On Wed, Mar 28, 2018 at 1:40 PM, Nutting, Phil  
> <[log in to unmask]>
> wrote:
>
>> Respected colleagues,
>>
>> I was just asked a question to which I could not put a number.
>>
>> In the case of needing to fix a circuit board "right now" to fill the
>> income stream there should be a logical point at which the reworks  
>> have
>> become too extensive for production boards beyond the "right now"  
>> need and
>> the board should be revised to eliminate the reworks.
>>
>> Is there an IPC or MIL standard that suggests a limit on the  
>> number of or
>> amount of rework allowed on a circuit board before it should be  
>> revised?
>>
>>
>> Phil Nutting  |  HVP Senior Development Engineer   |  Excelitas
>> Technologies Corp
>>
>> Lab: +1 978.224.4332   |  Office: +1 978.224.4152
>> 35 Congress St, Salem, MA  01970 USA
>> [log in to unmask]<mailto:[log in to unmask]>
>> www.excelitas.com<http://www.excelitas.com/>
>>
>>
>> [Excelitas R_emailsig]
>>
>>
>> Please consider the environment before printing this e-mail.
>> ________________________________
>> This email message and any attachments are confidential and  
>> proprietary to
>> Excelitas Technologies Corp. If you are not the intended recipient  
>> of this
>> message, please inform the sender by replying to this email or  
>> sending a
>> message to the sender and destroy the message and any attachments.  
>> Thank
>> you.
>>
>
>
>
> -- 
> Bhanu Sood
> Tel: (202) 468-8449

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