We have spent a lot of time on this also. We do x-ray everything inline
and have adopted 50% as the void limit for the cooling plates of QFN's as
our default in workmanship. Heat transfer requirements of the part may
require tighter limits and be documented for that product.
We epoxy fill and plate over all vias in the cooling plate, so unlike the
photo on page 18 - no open vias.
We have had great success with the solid pad and print area is key. You
want to cover about 60% to 70% of the area to keep the void area safely
below you limit. The suggested stencil picture on page 17 may work, but
with that many grids it is tough to get a coverage of around 60% to 70%.
For most smaller QFN's a grid of 2 x2 works best for us. It is best to
test the stencil apertures as this must also work with the amount printed
on the signal pins.
Make sure QFN voids like this aren't actually insufficient print coverage.
Roger Mack P.Eng.
Manufacturing Specialist
Parker Hannifin Canada
Electronic Controls Division
1305 Clarence Avenue
Winnipeg, MB R3T 1T4 Canada
direct 204 453 3339 x7373
[log in to unmask]
www.parker.com/ecd
From: Guy Ramsey <[log in to unmask]>
To: <[log in to unmask]>
Date: 2018-01-08 10:26 AM
Subject: [TN] solder voids - QFN belly pad
Sent by: TechNet <[log in to unmask]>
We are having trouble with a lot of boards.
We are seeing excessive voids like the ones on page 18 of this
presentation.
https://urldefense.proofpoint.com/v2/url?u=https-3A__www.google.com_url-3Fsa-3Dt-26rct-3Dj-26q-3D-26esrc-3Ds-26source-3Dweb-26cd-3D1-26ved-3D0ahUKEwj27JnJ38HYAhUF5YMKHWYICvcQFggpMAA-26url-3Dhttps-253A-252F-252Fwww.eptac.com-252Fwp-2Dcontent-252Fuploads-252F2012-252F06-252Feptac-5F07-5F18-5F12.pdf-26usg-3DAOvVaw2OX6J-5FYRqkuNUNNgDBvmwZ&d=DwIBaQ&c=zQLjxGaFENyz7VqOLRV_eQ&r=MTRQzKHrCCjgWzO_2fNMPjXUAeXe2IKt2DAIM9Q7PbA&m=HTryF-M_lvSHzqCszzIZ_UKKoCa9tYeOlDa0ngUHuZ8&s=8SAYbi6rfvdeiLoHzWO9k2YQqKHTv0AFJxCuknKLZc4&e=
The vias are filled and plated. Anyone seen this, resolved it?
Guy
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