Hi Guy - can you define "excessive"? Currently the IPC-JSTD-001 has no
requirement for center pad voids. The IPC-7093 specification contains
guidance that the maximum voiding for the center pad should be 50%. There
is a IPC-JSTD-001 task group looking at the topic as there has been
significant discussion on what the maximum void value should be and what
the current published technical data supports. I can tell you that most of
the issue isn't solder joint reliability but component functional issues
which is a design component selection attribute and not a process
attribute. With that being said, the solder paste formulation has a huge
impact on the creation of voids provided you have addressed the "open via"
influences. Take a look at the 2017 SMTAI paper APT5.2 by Richard Coyle, it
will be very useful in your discussions.

Dave Hillman
Rockwell Collins
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On Mon, Jan 8, 2018 at 10:26 AM, Guy Ramsey <[log in to unmask]> wrote:

> We are having trouble with a lot of boards.
> We are seeing excessive voids like the ones on page 18 of this
> presentation.
>
> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=
> 0ahUKEwj27JnJ38HYAhUF5YMKHWYICvcQFggpMAA&url=https%3A%2F%
> 2Fwww.eptac.com%2Fwp-content%2Fuploads%2F2012%2F06%2Feptac_
> 07_18_12.pdf&usg=AOvVaw2OX6J_YRqkuNUNNgDBvmwZ
>
>
> The vias are filled and plated. Anyone seen this, resolved it?
>
>
> Guy
>