LED's are cool to the touch compared to other light sources.
If the heat sink is missing, they will de-solder in less than 60 seconds
due to heat build up on high output applications.

Same with the FET's.

Vacuum reflow made a tremendous difference to our production capabilities.
Since the point of the line was reliable high volume light output, it was
acquired.
It reduced capacity.
Better to meet 99.9% yield at a slower rate than thruway a lot due to low
yield.
The new x-rays with automated void calculation helped reduce line support.
Errors were set up based rather than over time, first articles fully
inspected and tested prior to starting line.
Only 1 paste in house in cartridges with strict timing controls helped.

Prior lines had in line x-ray inspection for mixed signal product.
No voids on pad was more likely bad solder joint as previously stated with
the target of 50%.

On Mon, Jan 8, 2018 at 12:58 PM, Yuan-chia Joyce Koo <[log in to unmask]>
wrote:

> few place to look for the voids on ground plane: (1) via outgas - limited
> floor life of the board or bake the board.  (2) via poor wetting - normally
> filled via might using epoxy, it outgas and non-wet... Check via fill
> material and solder compatibility (3) Ground plane of the board sink too
> much heat (slow reflow process at ground plane) - change pre=heat.  (4)
> stencil print pattern - use "X" pattern and pick and place using "over
> travel" rather than drop - push the part down a bit... make sure no parts
> tilt (solder paste 65-68% coverage with channel allow flux to escape).  (5)
> you need to know the parts inside structure,  if it is small, no problem,
> if it consists of multiple ground, you need to make sure uniform coverage
> of solder under the parts (my spec used to be no 20% void in any
> guardroom,  with overall <30% to avoid any thermal runaway of the parts -
> you need to know your design... e.g. 3 thermal vias connect to a particular
> plane, if all three are not soldered, what will be the impact, not only
> thermal, but could be any electrical impact?)... etc.etc.  IMHO.
> Best of luck.
> jk
>
> On Jan 8, 2018, at 11:26 AM, Guy Ramsey wrote:
>
> We are having trouble with a lot of boards.
>> We are seeing excessive voids like the ones on page 18 of this
>> presentation.
>>
>> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&c
>> d=1&ved=0ahUKEwj27JnJ38HYAhUF5YMKHWYICvcQFggpMAA&url=https%
>> 3A%2F%2Fwww.eptac.com%2Fwp-content%2Fuploads%2F2012%2F06%
>> 2Feptac_07_18_12.pdf&usg=AOvVaw2OX6J_YRqkuNUNNgDBvmwZ
>>
>>
>> The vias are filled and plated. Anyone seen this, resolved it?
>>
>>
>> Guy
>>
>