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December 2017

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Subject:
From:
Wayne Showers <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Wayne Showers <[log in to unmask]>
Date:
Wed, 20 Dec 2017 17:47:07 -0600
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Generally people will plug either their own products or what has worked for them.  We use multiple platforms as each platform often leaves a little to be desired.  Aegis, Pentalogix, Graphicode and others offer different options and results.  Oftentimes a new name emerges that has a new take that emerges into the market space or other products take a hit because they move to an undesirable platform.  
One such platform that I used to use but cannot use any more because it is now web-based only is Quik-fit.  This is an easy optimizer for panel layout and yield which while not as important for rapid prototyping is a larger factor in volume as PCB is almost always a top 5 price driver.

Most pick and place equipment have libraries built in which overlay the recommended apertures to the provided apertures.  What they don't do, or at least I have not found any that do, is provided for mixed aperture review, e.g partial gang relief of soldermask.  This one is a nuisance as for as much as the solder mask can float up, solder is very capillary and creates a balled up mess.
Another factor is what stencil design factors are being used.  Solder balls under parts and factors such as placement deformation are consistent defect drivers.
As for the other defects described, a good ICT or Probe coverage map can uncover most of these.  You may want to ask, assuming you are doing some level of ICT or Probe Testing, how the polarized parts are being verified.  Oftentimes a 'non-standard' test such as forward and reverse voltage on a capacitor will quickly pin-point a polarity error.

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