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November 2017

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Subject:
From:
Wayne Thayer <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Wayne Thayer <[log in to unmask]>
Date:
Wed, 22 Nov 2017 19:24:21 -0800
Content-Type:
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That is a VERY difficult problem! You'd like the board to be powered during
this test so you can see how well the coating protected it. Well,
condensation looks simple when your looking at a glass of beer, but that's
not a good model for a powered-up circuit board!

I haven't seen attempts to correlate stuff like conformal coat surface
energy vs droplet size, or the multitude of other parameters which this
would have to contend with.

The best study I saw was with coated unpopulated boards using a nice
consistent test pattern. These were mounted on a thermal plate at a
well-controlled temperature while voltage was applied (the patterns were
inter-digitated traces (can't remember if they used vias too, but i think
not). My recollection is that the setup was placed in a large humidity
chamber maintained at 85% RH (can't go much higher and stay in control).

They were able to see differences between the conformal coats they tried.
But this misses out on all of the other factors due to spray application of
a highly variant surface.

Wayne

On Wed, Nov 22, 2017 at 2:46 PM, Richard Kraszewski <
[log in to unmask]> wrote:

> Other than what is written in IPC CC830 for thermal shock  and MIR testing
> , is anyone away of  any  industry standard that addresses the
> functionality of coating  or devices  when exposed to condensation?
>
> I have looked  at the IP Code for water ingress but all of that water
> testing  seems too invasive & harsh for what I am looking for.
>
> https://en.wikipedia.org/wiki/IP_Code
>
> Something in IEC perhaps.
>
> Rich  Kraszewski
> Senior Staff Process Engineer
> Plexus Engineering Solutions
>
>
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