I’d be cautious extracting roughness limit recommendations off a design guide from 2007. There’s been extensive process development in drilling, laminate, processing and acceptance requirements, that I would rely more on the current version of the 601X series specifications (6012, 6013, 6018). None of them have 'hole wall roughness' as an attribute for pass/fail, but rather dielectric removal (which has a wicking component), etchback, min plating thickness and others in section 3.6 of 601X. The performance criteria cited in those specs in not hole diameter dependent. I’d say if you have 1 mil roughness you better have a plating process (like pulse plating in some cases) that levels out that roughness into a sealed hole wall without thin areas that violate the min thickness requirement.


José (Joey) Ríos, Sr QA Engineer
Mission Assurance Manager
Kavli Institute for Astrophysics & Space Research
Massachusetts Institute of Technology
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(617)324-6272




> On Sep 6, 2017, at 5:54 AM, Deng RongJun <[log in to unmask]> wrote:
> 
> Fellow TechNetters:
> 
> IPC DR-572A 9.3.3 has defined that the maximum allowable roughness is recommended to be 25 μm. Is this for all size drilled holes? 
> Sometimes I head from PCB fabricator that the drill hole roughness is depends on hole size, ex.: 0.5-0.8mm drill hole roughness <25.4 μm, 0.8-2.6mm drill hole roughness <30 μm.
> The hole wall roughness will cause blow hole in solder joint during wave or selective soldering if moisture go in to PCB inside. So we need to control the roughness on hole wall surface.
> Is anyone have experience on this?   What roughness is reasonable for PCB hole?
> 
> Best regards
> Deng