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August 2017

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Subject:
From:
Jose A Rios <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Jose A Rios <[log in to unmask]>
Date:
Wed, 23 Aug 2017 21:01:53 +0000
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Hey Victor, just fyi, J-STD-003C w Amendment 1 (Sept 2014), is the most current. So unless you’re under contract by your customer to do solderability testing to J-STD-003B (or supplying to MIL-PRF-31032, which last I knew has not adopted 003C yet), you may need to catch up with the current versions.
Anyhow paragraph 4.2.3.2 of 003B gives you the option of one of three test specimens: a 2”x2” board cutout containing the features of interest (30 holes for example), an S coupon (Fig 4-2 for thru hole soldering, or Fig 4-3 for surface, although M coupon is widely accepted as a surface solderability test specimen), or the entire board if you can tolerate loosing a board to this test AND the entire board is immersible (fits) in the solder pot. It doesnt dictate a preferred sample from the 3 listed, you have to choose which one represents the lot being tested. Boards with no thru hole soldering, do not require thru hole solderability testing. If the application is surface mount (no thru holes), 6012 allows for solderability testing by using an M coupon (no thru holes).

Also, 003B does not distinguish between testing a thru hole board any different than an HDI board, the solder float test method is the same (think of it as you’re testing the solderability of the finish metallurgy as applied). Often the final finish process is exactly the same for a variety of product types (same chemistry parameters, dwells, temperatures, etc), so when you look at it from that angle it makes sense that the test method is the same for varied product types..

Some board users are phasing out of the solder float method because of its ‘poor gage r&r’, but the solder float method is still a valid method for acceptance, unless otherwise specified on a drawing or PO.

I hope this is useful, let me know otherwise.

José (Joey) Ríos, Sr QA Engineer
Mission Assurance Manager
Kavli Institute for Astrophysics & Space Research
Massachusetts Institute of Technology
[log in to unmask] <mailto:[log in to unmask]>
(617)324-6272



> On Aug 23, 2017, at 4:11 PM, [log in to unmask] wrote:
> 
> Fellow TechNetters:
> 
>   I am surprised that no PWB cross section guru has responded to my inquiry for information on the above stated topic.   Perhaps the second time is a charm.   I am trying to do diligence on this HDI job request.
> 
> Victor,
> 
> From: Hernandez, Victor G
> Sent: Wednesday, August 23, 2017 7:35 AM
> To: TechNet E-Mail Forum <[log in to unmask]>
> Cc: Hernandez, Victor G <[log in to unmask]>
> Subject: IPC-J-STD-003B, 4.2.3.2 Test Specimen
> 
> Fellow TechNetters:
> 
>   I am requesting for assistance/clarification on the above stated standard section.   This was in the hay days when PWB utilized PTH every 100 thousands centers.   That was a lot of interconnects.   Now that we have HDI what is the criteria for the ROI on the required specimen as per Figure 4-2 of the same standard.
> 
> 4.2.3.2 Test Specimen The test specimen shall be in accordance with 1.7. The test  specimen shall be a portion of the printed board not greater than 50 x 50 mm [1.97 x 1.97 in], the suggested test specimen, or the complete board if it is smaller than this size. The minimum number of holes to be tested is 30 per test lot. If there are not at least 30 holes in the test specimen, additional specimens shall be tested until at least 30 holes have been tested (see Figure 4-2 Through-Hole Test specimen). Test specimen preparation shall be in accordance with 3.4.
> 
> Victor,

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