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Subject:
From:
Yuan-chia Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Yuan-chia Joyce Koo <[log in to unmask]>
Date:
Mon, 7 Aug 2017 08:05:18 -0400
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text/plain
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text/plain (38 lines)
i believe ipc got std for esd... you better treat as esd sensitive -  
embedded components are gaining popularity now.  if you set up  
internal std.  you should do it now as esd sensitive PCB  
regardless...IMHO.
On Aug 7, 2017, at 6:43 AM, GRIVON Arnaud wrote:

> Hello TechNet,
>
> Here is a query I got that falls more on PCB design side and  
> slightly outside my boundaries...
> Trying the TechNet shortcut as this is probably the quietest week  
> of the year with most people being in vacation...
>
> The question is on the rules and requirements regarding the ESD  
> susceptibility symbol at PCB level.
> The yellow/black symbol is well-known for electronic components,  
> but how should it be implemented at PCB level ?
> All PCB assemblies include ESD sensitive components, so shall it be  
> done systematically or can it be missed ?
> If needed, how should it be done : by affixing labels or are etched  
> symbols of PCB also an option ? Does it have to be close to the  
> most ESD sensitive part locations or is it intended to be a global  
> marking for the whole PCBA ?
>
> As far as I can see, the ANSI/ESD S8.1 standard mentions marking at  
> PCB level (Quote : "The ESD susceptibility symbol should be used on  
> assemblies and devices that have a sensitivity to ESD events") but  
> is clearly more focused on marking at the component packaging level  
> (Quote : "The symbol may be incorporated on a sticker used to close  
> or seal ESD protective packaging to indicate that materials inside  
> the package are ESD susceptible").
>
> Thanks in advance for your any clue.
>
> Best regards,
>
> Arnaud Grivon

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