Thanks for the deeper explanation.



For “narrow” traces embedded in pre-preg, the common assumption is that the dielectric thickness above the trace (or below if the pre-preg is on that side) will be the “cured sheet value” of the pre-preg less the trace thickness. For “fat” traces, you don’t subtract the trace thickness. Obviously there is a transition between “narrow” and “fat”, but it usually gets lost in the noise of etch accuracy and pre-preg standard thickness variation. Other variables affecting that are pre-preg flow viscosity, lamination time/pressure/temperature, and press pad thickness. Bottom line is that hitting within 10% of target is doing pretty well, and getting tighter than that will require careful process control and calibration. Another variable is how well the “ground planes” are electrically connected to the signal generator and receiver (via construction and placement).



I think I’ve seen Polar’s output, but if it is using the area, perhaps it is trying to generate the “narrow”/”fat” tweaks, in any case I’m not seeing that being able to eliminate calibration if high accuracy is needed.



Wayne





From: Pradeep Menon [mailto:[log in to unmask]]

Sent: Wednesday, May 24, 2017 7:14 AM

To: Wayne Thayer; TechNet E-Mail Forum

Subject: RE: Copper area for impedance calculations



Thanks Wayne for the reply.



We use Polar speed stack for impedance calculations. Our query was basically to more accurately determine the dielectric thickness between the layers which will influence the impedances, especially the differential impedances. The copper thickness and the copper area will have a bearing on that. It is just not ground alone. When there are signals wherein the copper area is less, more resin goes into fill the gaps between the tracks which might reduce the dielectric thickness between the layers. While in a ground layer, as there is nothing to fill, the dielectric thickness would be relatively higher.



Hope this gives a better picture on our concern



Regards



Pradeep





From: Wayne Thayer [mailto:[log in to unmask]]

Sent: Wednesday, May 24, 2017 7:32 PM

To: TechNet E-Mail Forum; Pradeep Menon

Subject: RE: Copper area for impedance calculations



Greetings Pradeep-



What impedance formula are you using? For traveling wave impedance, the common formulas don't have copper area in them. (They do have width and thickness, so you could calculate area, but your context seems to be the copper area on something like a ground plane)



Wayne Thayer



-----Original Message-----

From: TechNet [mailto:[log in to unmask]] On Behalf Of Pradeep Menon

Sent: Tuesday, May 23, 2017 9:19 PM

To: [log in to unmask]<mailto:[log in to unmask]>

Subject: [TN] Copper area for impedance calculations



Dear All



Wanted a little more clarity on the copper area that is usually considered for inner layers while calculating impedance. Is it copper area in individual circuit or copper area for each layer after panelisation. There can be instances wherein the two can have quite a good difference which may result in dielectric variation and hence the impedance calculations also.



Can you please suggest what is the commonly followed practice.



Rgds



Pradeep

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