TECHNET Archives

April 2017

TechNet@IPC.ORG

Options: Use Monospaced Font
Show Text Part by Default
Show All Mail Headers

Message: [<< First] [< Prev] [Next >] [Last >>]
Topic: [<< First] [< Prev] [Next >] [Last >>]
Author: [<< First] [< Prev] [Next >] [Last >>]

Print Reply
Subject:
From:
"Upton, Shawn" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Upton, Shawn
Date:
Mon, 24 Apr 2017 12:43:01 +0000
Content-Type:
text/plain
Parts/Attachments:
text/plain (1 lines)
I've had vendors ask if a via was via in pad.  Sometimes they can't read design intent.  A simple "no" fixes that.



I suspect small vias are more often than not filled.  They are either via in pad or used for thermal reasons.  Otherwise they'd be avoided and lower cost vias used instead.



Shawn Upton





-----Original Message-----

From: TechNet [mailto:[log in to unmask]] On Behalf Of Nagaraj Shanmugam

Sent: Monday, April 24, 2017 3:14 AM

To: [log in to unmask]

Subject: [TN] Via fill - what parameters drive via filling?



All,



I have a PCB of thickness 60mils(0.060"/1.53mm) and has a smallest through hole via is 4 mil(0.004"/0.1mm). These are NOT  Via in pad.

The aspect ratio here is 15.



Fab vendors asking for via fill here. Does these 4 mil via need to be filled?  I have boards done without fill for a 8mils drill on a 120mil thick board (Aspect ratio is 15 here). 



Appreciate to help to understand what parameter or factors determine the filling here.



Thanks,

Nagaraj.


ATOM RSS1 RSS2