Any baking before reflow ?
Got situation like that due to moisture entrapped in PCB and reflow temperature for Lead Free
Gabriele
-----Messaggio originale-----
Da: TechNet [mailto:[log in to unmask]] Per conto di Carl Van Wormer
Inviato: mercoledì 26 aprile 2017 16:29
A: [log in to unmask]
Oggetto: Re: [TN] PCB delamination at area with ground-plane cutout
The delamination was noticed by the CM, after running the board (SMT components on 2 both sides) through their re-flow processing. They claim to have done an appropriate job of thermal profiling on this new board. The resultant product looks good, except for the delamination areas.
The delaminated pictures were sent to the PCB fabrication house, which resulted in the response about adding copper to the cut-out areas.
Our fabrication notes state:
All materials used in PCB construction to be RoHS2 Directive 2011/65/EU compliant and lead-free assembly compliant.
Laminate and Prepreg (B-stage) to be in accordance with IPC-4101/126, /129.
Is there a way to tell, by looking at the PC board, what temperature rated laminate was used to make it?
Thanks,
Carl
Carl B. Van Wormer, P.E., AE7GD
Senior Hardware Engineer
Cipher Engineering LLC
21195 NW Evergreen Pkwy Ste 209
Hillsboro, OR 97124-7167
503-617-7447x303
[log in to unmask]<mailto:[log in to unmask]> http://cipherengineering.com<http://cipherengineering.com/>
From: Toby Carrier [mailto:[log in to unmask]]
Sent: Wednesday, April 26, 2017 7:18 AM
To: Carl Van Wormer <[log in to unmask]>
Subject: Re: [TN] PCB delamination at area with ground-plane cutout
Carl,
You mention this is happening during "high heat", what is the high heat scenario? What PCB material are you using and do you know their thermal profile?
Thanks,
Toby Carrier
On Apr 26, 2017 10:13 AM, "Carl Van Wormer" <[log in to unmask]<mailto:[log in to unmask]>> wrote:
Ignoring the electrical characteristics of the plane cutout and reduction of capacitive coupling to the rest of the system, my main question is trying to understand why (and if) adding copper to that area (on layers 2 and 5) will reduce the possibility of delamination. Has anybody else seen declamation caused by copper missing on inner layers of a 6-layer board?
Thanks,
Carl
Carl B. Van Wormer, P.E., AE7GD
Senior Hardware Engineer
Cipher Engineering LLC
21195 NW Evergreen Pkwy Ste 209
Hillsboro, OR 97124-7167
503-617-7447x303<tel:503-617-7447x303>
[log in to unmask]<mailto:[log in to unmask]> http://cipherengineering.com
-----Original Message-----
From: Upton, Shawn [mailto:[log in to unmask]<mailto:[log in to unmask]>]
Sent: Wednesday, April 26, 2017 7:02 AM
To: TechNet E-Mail Forum <[log in to unmask]<mailto:[log in to unmask]>>; Carl Van Wormer <[log in to unmask]<mailto:[log in to unmask]>>
Subject: RE: PCB delamination at area with ground-plane cutout
I have to wonder why the plane was pulled back. Looks like a DB9, so I'm thinking, low speed signals, possible RS232. But it could be some high impedance circuit where capacitive loading is a big problem. Perhaps not. Perhaps the pullback was done not to limit capacitive effects on the traces on that DB9, just a pullback to prevent coupling, as a plane wasn't required. Just guessing, so as to not impact circuit performance.
If low capacitance is required, it might be a bit more work than just adding a split plane or thieving, as it couldn't be added under the traces--but it could be brought "near" for the desired effect. But if it was just a "we don't need a plane here, just remove it" then a split plane should be easy enough to use, with a full or crosshatched pour.
Shawn Upton
Section Head, Test Engineering
Sensors Business Unit
Allegro MicroSystems, LLC
[log in to unmask]<mailto:[log in to unmask]>
603.626.2429<tel:603.626.2429>/fax: 603.641.5336<tel:603.641.5336>
-----Original Message-----
From: TechNet [mailto:[log in to unmask]<mailto:[log in to unmask]>] On Behalf Of Carl Van Wormer
Sent: Wednesday, April 26, 2017 9:51 AM
To: [log in to unmask]<mailto:[log in to unmask]>
Subject: [TN] PCB delamination at area with ground-plane cutout
We received pictures from our contract manufacturer, marked to show delamination occurring in 2 areas on our 6-layer boards. The delamination areas were at the electrically isolated communication interfaces that were made with no copper on the power and ground planes to reduce capacitive coupling. The response from the PCB manufacturer is:
1)defect reason: we used our stock boards to run the thermal shock test, we see the de-lam is only taking place in the two areas without copper (pic 1.jpg),
There is insufficient glue in this area that happened during lamination and that is why the de-lam is happening when the customer is assembling under the high temp, 2)correction action: if the customer needs us to remake, we suggest to modify the design a little, pls see pic 2.jpg, we will fill the marked area with solid copper .
Please confirm if a remake is needed, we will arrange right away.
Steve Gregory has posted the pictures at:
http://stevezeva.homestead.com/Carl1.jpg (board cut open for evaluation at board house)
http://stevezeva.homestead.com/Carl2.jpg (picture showing where they want to add copper)
(and 2 pictures of the delaminated areas) http://stevezeva.homestead.com/Delamination_-_is_it_caused_by_missing_ground_plane__1_.jpg
http://stevezeva.homestead.com/Delamination_-_is_it_caused_by_missing_ground_plane__2_.jpg
Question to the group: Will adding copper on the electrically isolated open areas eliminate this type of delamination? We could add the copper, but not connect it to the system ground.
Thanks,
Carl
Carl B. Van Wormer, P.E., AE7GD
Senior Hardware Engineer
Cipher Engineering LLC
21195 NW Evergreen Pkwy Ste 209
Hillsboro, OR 97124-7167
503-617-7447x303<tel:503-617-7447x303>
[log in to unmask]<mailto:[log in to unmask]><mailto:[log in to unmask]<mailto:[log in to unmask]>> http://cipherengineering.com<http://cipherengineering.com/>
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