Great question Jack!
From a manufacturing perspective, It is very difficult to consistently print and attempt to fill vias with only soldermask while keeping the pad clear simultaneously. Depending on the hole size you may not plug the hole at all with solder mask and there is always the possibility that the mask would mis-register and you would end up with mask on your solderable pads regardless.
Your corollary question with regards to minimizing via size: we have seen finished holes less than 0.006" in diameter still readily wick solder away from a BGA so you really need to ensure that the hole is plugged consistently. Tom's suggestion to hole fill and planarize is the best option to ensure the vias are consistently plugged. IPC 6012 D section 3.6.2.18 requires a minimum hole fill of 60% for class 2 and 3 applications. Even 60% hole fill can be a challenge when finished hole sizes fall below 0.010" with high aspect ratio. If you decide to hole fill, check with your supplier to see what percentage they can consistently fill.
Good luck!
Ron Nowak
Electronic Packaging Applications, RMS-Owego Operations
Lockheed Martin Corporation
1801 state route 17C, Owego, NY, 13827-3998
O 607-751-2089 | M 607-427-0870
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Tom Brendlinger
Sent: Thursday, December 15, 2016 11:45 AM
To: [log in to unmask]
Subject: EXTERNAL: Re: [DC] Plugging Thermal Via Holes with Soldermask?
We recently used the following notes to attempt to do precisely what you're
describing:
12.2 All vias 0.020" in diameter or less shall be plugged from top side prior to primary soldermask application per IPC-4761 Type III. Plug material shall be approved by Levant engineering before production begins.
12.3 Plugs in vias shall not protude above top of hole.
12.4 All plugged vias shall be filled at least 80% with fill.
12.5 Via plug integrity, fill percentage and protrusion shall be confirmed with a microsection of a representative quality conformance coupon
However, after soldering about 30% of the at-risk holes had solder flow-through. We didn't see bumps, just a thin layer of wetting, but we only had 16 boards populated in this run so I don't think we have enough data to show that we never would have that issue.
I am currently working with our PCB manufacturer to identify what happened, but in my opinion this isn't a fully manufacturable solution. I'm attempting to solve the same problem that you are, so I'm absolutely interested in any other way to do this.
--
Tom Brendlinger, CID
Electrical Engineer
Levant Power / ClearMotion Inc
Woburn, MA 01801
On Thu, Dec 15, 2016 at 11:10 AM, Jack Olson <[log in to unmask]> wrote:
> I'm looking at the various options for tenting/plugging/capping vias
> in
> IPC-4761 (Via Protection Guidelines). None of the options seem to
> address the thermal vias in power pads.
> We are trying to:
> 1) have a solderable pad, apply paste on that side (of course)
> 2) prevent solder from creating bumps on the heatsink side (of course)
> 3) avoid the cost of plugging/capping
>
> IPC-4671 states that all forms of one-sided via protection are NOT
> RECOMMENDED.
>
> So here's the question - I know I have seen a picture of a thermal pad
> in an IPC document where I could see vias with green mask material in
> them on the paste side (the component side), but the green stuff was
> only in the holes, which left the thermal pad exposed for soldering.
> I don't think this would be called TENTING because there's no mask on
> the pad. but is this an acceptable practice? Can I instruct a bare
> board fabricator to put mask in holes from the top side, but keep the pad clear?
> (I can't remember where I saw the picture!)
>
> If that's NOT an accepted practice, is there a way to design the hole
> big enough to plate but small enough to prevent solder flowing through
> the other side of the board? I couldn't find a discussion of that in
> the TechNet Archives
>
> thanks,
> Jack
>
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