Just provide a high x-ray image of the artifact in question as not to reveal confidential details. Not sure of the description you provided. Is the via in question part of the rigid are part of the flex. I have seen issues with via that interconnect through PWB laminate and internal flex region, plating issue....
Victor,
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Golemme
Sent: Monday, November 14, 2016 1:58 PM
To: [log in to unmask]
Subject: Re: [TN] Fixing Cracked via holes
Thanks everyone.
I'd like to summarize everything said, and answer all the questions in ways that don't reveal confidential info.
I'm looking at moisture ingress opportunities and moisture control prior to assembly since it's non-destructive and could provide a smoking (water)gun.
Wayne Thayer:
Drop a wire in the via and solder on ring or nearby pad. Not sure about reliability unless it’s a 2 layer board.
Scott Decker:
Drop a wire if it’s the same via. And wire up connections to internal planes.
Steven Kelly:
Whether or not PCBAs were pre-baked before SMT could have a factor.
jkoo@:
Need to find root cause.
Jose Rios:
isolated thin areas of plating that didn't hold up to thermal stress (requires DPA to diagnose)
plated copper properties (low elongation, less likely IMO)
it could mean there is partial plating voids (as plated)
Note sometimes ICT covers nets that aren't part of the bare board electrical test (IPC bare board net listing)
Questions:
Pre-bake? – investigating pre-assembly as well as shipping and storage conditions
TH or microvias?: TH
Two layer? multi layer (more than 2) rigid flex.
Thanks Again,
Stephen Golemme
Manufacturing Engineer, Makani
650-214-5647
solveforx.com/makani
On Fri, Nov 11, 2016 at 12:17 PM, Jose A Rios <[log in to unmask]> wrote:
> Possible root causes (seen 2 of the 3 in actuality); It could be
> isolated thin areas of plating that didn't hold up to thermal stress
> (requires DPA to diagnose), or plated copper properties (low
> elongation, less likely IMO). I've also seen where ICT covers nets
> that aren't part of the bare board electrical test (IPC bare board net
> listing). In the case of the latter, it could mean there is partial
> plating voids (as plated), not induced by thermal stress. I've seen
> this (rare), on 30:1 aspect ratio boards with 10-12 mil drilled holes
> with a 60K or so hole count so 1 hole out of hundreds of thousands in
> a lot, can have a single partial void thats hard to detect.
>
> Sent from my iPhone
>
> > On Nov 11, 2016, at 2:14 PM, Steve Golemme <[log in to unmask]>
> wrote:
> >
> > We have a couple of expensive first time build boards that failed
> > ICT in assembly due to what appears to be cracked vias. Adding
> > solder to the via hole seems to fix the issue.
> >
> > What are folks thoughts on plugging vias with solder to fix them?
> > What risks are we taking by adding solder vs another technique?
> > Could folks recommend alternate repair techniques that may provide
> > better thermal/vibration?
> >
> > Also, I'd love to hear up alternate possible root causes? This
> > problem screams insufficient plating during fab or thermal shock
> > during assembly, but I'd like to investigate all possible failure
> > modes. This is a multi-layer double sided SMT + wave rigid-flex PCB
> > and the cracking is on the rigid portion.
> >
> > Thanks,
> > Stephen Golemme
> > Manufacturing Engineer, Makani
> > 650-214-5647
> > solveforx.com/makani
>
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