solder mask should not consider as dielectric during design clearance
calculation.  IMO..
         jk
> Food for thought,
>
>    I have seen Field Return PWB in which a short was created between the
> PWB edge and the metal chassis /metal hardware.   Due to spacing
> clearance and solder mask thickness
>
> Victor,
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Yehuda Weisz
> Sent: Sunday, November 13, 2016 4:15 PM
> To: [log in to unmask]
> Subject: [TN] Copper to edge distance
>
> Hello  Technetters,
> For the beginning of the week I have a question to you that occupies me
> more and more lately, and it concerns one of the design guidelines -
> "distance of copper to edge".
>
> IPC-2221 specifies the minimum distance by design as 20 mils and raises
> this value as the voltage drop increases.
> Well, as PCBs become more and more dense, it becomes a very challenging
> task to convince designers to give up real-estate along the edges of the
> board.
> Their claim - if the manufacturer can work with a tolerance of +/-0.1mm,
> why do I need to keep a clearance of 0.5 mm along the edges.
> Most of the boards we are dealing with are for high reliability customers
> (class 2, class 3 type guys) and from what I have heard from other
> designers
> - no one goes below 20 mil. Some even keep a minimum of 40 mil along the
> edges.
>
> So - my question to you is simply - WHY ???
> Why did the spec. call for 20 mil minimum clearance??
> I do give reasons to the designers, involving reliability and so on but I
> feel that I might be missing the real point (or the fundamental reason).
>
> Could any/some of you, knowledgeable people, help me out on this??
>
> Thanks,
> Yehuda Weisz
>