Part of that is to have sufficient margin that takes into account layer to layer alignment during fab and its associated metal to edge clearance. Machining (from panel to individual board) takes up also some of that registration budget. If metal gets too close to an edge consider that laminate haloing from machining/routing can result (the 6012 haloing allowance assumes the 2221/2222 design guidelines were followed). Suppliers should be able to tell you how low can you go (metal to edge design spacing) before the minimum lateral spacing is violated, without exceeding the haloing allowances of 6012. 

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> On Nov 13, 2016, at 5:15 PM, Yehuda Weisz <[log in to unmask]> wrote:
> 
> Hello  Technetters,
> For the beginning of the week I have a question to you that occupies me more
> and more lately, and it concerns one of the design guidelines - "distance of
> copper to edge".
> 
> IPC-2221 specifies the minimum distance by design as 20 mils and raises this
> value as the voltage drop increases.
> Well, as PCBs become more and more dense, it becomes a very challenging task
> to convince designers to give up real-estate along the edges of the board.
> Their claim - if the manufacturer can work with a tolerance of +/-0.1mm, why
> do I need to keep a clearance of 0.5 mm along the edges.
> Most of the boards we are dealing with are for high reliability customers
> (class 2, class 3 type guys) and from what I have heard from other designers
> - no one goes below 20 mil. Some even keep a minimum of 40 mil along the
> edges.
> 
> So - my question to you is simply - WHY ???
> Why did the spec. call for 20 mil minimum clearance??
> I do give reasons to the designers, involving reliability and so on but I
> feel that I might be missing the real point (or the fundamental reason).
> 
> Could any/some of you, knowledgeable people, help me out on this??
> 
> Thanks,
> Yehuda Weisz