6012 guy here….
The design guides for pwb’s do not explicitly address this in terms of robustness. It only outlines (in IPC-2222A), three different levels of ‘design for manufacturability’ regarding pitch, in Table 9-1. The 3 levels of manufacturability (A, B, C) denote increased levels of build difficulty. Thats the extent to which the IPC design documents provide design guidance regarding pitch. So if you have a ‘C level’ design for a given attribute, assume the capability to provide for it is limited and would need to be confirmed by the supplier who’s building the board ahead of time. I would add that 2222A dates back to 2010, and theres been advances in laminates and fab processes that make Table 9-1 a bit dated.
On the fab side, eliminating requirements for positive etchback (aggressive plasma treatments to provide for innerlayer '3 point connections’), reduces the exposure to CAF.
José (Joey) Ríos, Sr QA Engineer
Mission Assurance
Kavli Institute for Astrophysics & Space Research
Massachusetts Institute of Technology
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> On Oct 7, 2016, at 10:29 AM, Theodore J. Tontis <[log in to unmask]> wrote:
>
> Nigel,
>
> CAF is more of a manufacturing defect due to drill bits pulling or breaking glass fibers in the laminate material. Placing via's close together increases the likelihood CAF will occur.
>
> With HDI designs via prep is different. Most microvias are not drilled completely through the board, they are stacked. They can also be laser formed instead of drilled. Ask the board supplier which process they are using.
>
> Also, there is CAF resistant laminate material to help reduce CAF from occurring. If there is concern, reach out to your board supplier and ask them if they can provide you with CAF resistant laminate or at least share your concern with them. Your board supplier has a wealth of knowledge they would love to share with you.
>
> No, there is no design guideline that will provide the minimum gap to make a robust design. There are far too many variables that would go into that decision making process. To name a few, end use environment, min voltage clearance, laminate material, .....
>
> Best advice is to reach out to the board supplier and share your concerns. Most laminate suppliers have performed tests on their materials and can provide data. If it is a mission critical Design I would suggest creating test coupons and evaluating the materials yourself.
>
> Ted
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Nigel Burtt
> Sent: Friday, October 07, 2016 7:50 AM
> To: [log in to unmask]
> Subject: via hole wall-wall mimimum separation
>
> Because of mechanisms like CAF/CFF I have in mind a paper I read some years ago that quoted some work by Sun Microsystems that suggested via hole wall-wall distances in a design should aim to be minimum 0.5mm wherever possible and with the holes staggered as much as possible.
>
> In today's HDI PCB world a wall-wall gap of 0.5mm seems like a big ask for the designer. Looking at the IPC-9253 and IPC-9254 CAF test PCBs, these have wall-wall spacings that vary between 0.15 and 0.89mm, so I assume the 0.15mm end is intended to represent real-life design and not just a practical PCB fabrication limit?
>
> Is there an IPC PCB design guideline which points to what a designer should aim for as a minimum gap to make the design as robust as it can be?
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