Nigel,



CAF is more of a manufacturing defect due to drill bits pulling or breaking glass fibers in the laminate material. Placing via's close together increases the likelihood CAF will occur.  



With HDI designs via prep is different. Most microvias are not drilled completely through the board, they are stacked. They can also be laser formed instead of drilled.  Ask the board supplier which process they are using.



Also, there is CAF resistant laminate material to help reduce CAF from occurring. If there is concern, reach out to your board supplier and ask them if they can provide you with CAF resistant laminate or at least share your concern with them. Your board supplier has a wealth of knowledge they would love to share with you.



No, there is no design guideline that will provide the minimum gap to make a robust design. There are far too many variables that would go into that decision making process. To name a few, end use environment, min voltage clearance, laminate material, .....



Best advice is to reach out to the board supplier and share your concerns. Most laminate suppliers have performed tests on their materials and can provide data. If it is a mission critical Design I would suggest creating test coupons and evaluating the materials yourself.  



Ted





-----Original Message-----

From: TechNet [mailto:[log in to unmask]] On Behalf Of Nigel Burtt

Sent: Friday, October 07, 2016 7:50 AM

To: [log in to unmask]

Subject: via hole wall-wall mimimum separation



Because of mechanisms like CAF/CFF I have in mind a paper I read some years ago that quoted some work by Sun Microsystems that suggested via hole wall-wall distances in a design should aim to be minimum 0.5mm wherever possible and with the holes staggered as much as possible. 



In today's HDI PCB world a wall-wall gap of 0.5mm seems like a big ask for the designer. Looking at the IPC-9253 and IPC-9254 CAF test PCBs, these have wall-wall spacings that vary between 0.15 and 0.89mm, so I assume the 0.15mm end is intended to represent real-life design and not just a practical PCB fabrication limit?



Is there an IPC PCB design guideline which points to what a designer should aim for as a minimum gap to make the design as robust as it can be?