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October 2016

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[log in to unmask], "Theodore J. Tontis" <[log in to unmask]>
Date:
Fri, 7 Oct 2016 09:49:34 -0500
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TechNet E-Mail Forum <[log in to unmask]>, Nigel Burtt <[log in to unmask]>
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Nigel Burtt <[log in to unmask]>
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Thanks Ted

I'm aware of the phenomena and the material choices to minimise the risk.

Clearly close spacing is sometimes driven by component technology and pitch, but I wondered if at the PCB design stage there was an industry best practice guideline or  DRC to look in more detail at smaller wall-wall spacings in a prepared design before it goes to fab and increase them to "x" wherever possible to further improve robustness.

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