agree, spacer works well. (depend upon what you can lay your hands  
on).  you don't see that much QFN failure due to (1) the device  
substrate - high density is made by BT substrate or high temp FR4 or  
(2) made by Cu-lead frame.  very much match up to the PWB in terms of  
CTE. Can not be said for LTCC... some large LTCC you can  mount  on  
polyimide with full temp Tg 220 C, without any reliability problem,  
but move to FR4 with Tg of 150-160,  you got problem... using corner  
large  dummy SJ with Pb rich solder and proper stand-off, you can get  
away somehow for the limited size  (and location of the  PWA).  Pb  
rich got this wonderful properties of self healing under cyclic  
stress upon  TC,  you can get away with newbie's silly mistakes a  
bit,  without put too much stress on the part (if you pot it... as  
usually the newbies pop out "solution" - if you have LTCC, usually,  
you are deal with some  kind of thermal part, potting it didn't   
really help to dissipate heat... of course, the process guys didn't  
appear to  be "notice any difference"_ ).  Don't use thickness  of  
solder as the trick unless you got pushed to the wall (even that,  
jump the wall if you can)... warning: with push to >10Gb/s and more  
Radar come to the driverless car, you got see more LTCC down  to the   
line... thanks  god,it would be someone else worry now...
I am glad Wayne most agree with me... it made my day... thanks.
         jk
On Aug 30, 2016, at 6:09 PM, Wayne Thayer - EXT wrote:

> As usual, I agree MOSTLY with Joyce, but ...
>
> I've not seen a lot of success trying to increase joint height by  
> using preforms to add more solder--usually that just makes shorts.  
> You can try to use a spacer, which will work as long as you pay  
> attention to the relative thermal expansion coefficient of the  
> spacer vs. the solder.
>
> In previous posts, I've railed against the IPC cop-out expression  
> "evidence of wetting"--especially for class 3 assemblies which have  
> parts with pads completely beneath the part. Also note that the  
> "evidence" does not need to include wetting to the toe of the lead  
> (the only part you have a prayer of seeing). HOWEVER, history seems  
> to show that these concerns aren't as serious as some of us old  
> geezers thought they would be. At least, I'm unaware of huge  
> numbers of solder joint failures on QFN parts attributable to  
> inadequate joint height, even in prototyping runs. And other parts  
> with no leads, such as large ceramic capacitors do not seem to  
> suffer from pre-mature failure due to inadequate solder beneath the  
> part.
>
> Wayne
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]] On Behalf Of Yuan-chia Joyce  
> Koo
> Sent: Tuesday, August 30, 2016 2:58 PM
> To: [log in to unmask]
> Subject: Re: [TN] Solder under SMD Pads thickness Mins and Maxes.
>
> why you need max  min?  if  you need for reliability reason  using  
> Pb rich solder to relief some  strain for example, you will need to  
> have preform  to define min.  thickness.  Unless your design is  
> pushed to the limit - extreme temp included, or  try to fix  
> someone's crappy design at late stage, you don't use  that...  you  
> will need (1) process control data, (2) FEM for thermal expansion  
> analysis for example,  etc.- not difficult if only a bit off, but  
> it would very difficult if it is way off the mark (like someone  
> selected a low Tg, high CTE board to cut cost... scream bloody  
> murder...).
> On Aug 29, 2016, at 4:12 PM, Decker, Scott UTAS wrote:
>
>>    For some reason, I thought I saw a spec that mentioned what the
>> minimum and maximum solder thicknesses are or can be between the
>> component termination and the board pad. I looked through the J-
>> Standard for soldering and could only find a reference to Dimension
>> "G" note 3 which reads "Must show evidence of wetting." but no  
>> minimum
>> or maximum. Can someone point me to the spec if there is one, for  
>> this
>> soldering aspect of an assembly, or tell me I'm seeing things that
>> don't exist... Thanks in advance...
>> Happy Monday to all!
>>
>> Scott Decker - Senior Analyst, Drafting & Design Services CID+ -
>> Electronic Systems Center UTC AEROSPACE SYSTEMS
>> 3445 S. 5th Street, Suite 170, Phoenix, AZ 85040 U.S.A.
>> Tel: 602 308 5957  FAX: 602 243 2347
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>>
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