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June 2016

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Subject:
From:
David Hillman <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, David Hillman <[log in to unmask]>
Date:
Wed, 22 Jun 2016 07:40:55 -0500
Content-Type:
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Hello Mumtaz - I recommend doing the JSTD-002 Surface Mount Simulation Test
(Test S) as the QFN is a SMT component and the testing will provide a
better representative assessment of your production soldering interactions.
Testing SMT components using PTH techniques is valid but the soldering
dynamics can play a role in causing "false negatives" depending on a couple
of solidification factors. That is the reason the JSTD-002 committee added
surface mount testing options for SMT component technologies.

Dave Hillman
Rockwell Collins
[log in to unmask]

On Tue, Jun 21, 2016 at 6:42 PM, Mumtaz Bora <[log in to unmask]> wrote:

> Hello Technet team,
>
> We have a laminate based QFN package with ENIG plating on terminations.
>  Using lead based paste Sn63/Pb37,  we fail solderability test per
> JESD22B102E (dip and Look test) and also per J-STD-002 method B (dip and
> Look test). However,  we passed reflow solderability test using  lead free
> paste (SAC 305) per method JESD22B102E . Due to product requirements, we
> have to use eutectic Sn63/Pb37 solder paste.  The reflow oven is convection
> air . If anyone had this issue and can share some insight or inputs will
> be  much appreciated.
>
>
>   Thank-you,
>   Mumtaz
> 858-795-0112
>
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