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Subject:
From:
Yuan-chia Joyce Koo <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Yuan-chia Joyce Koo <[log in to unmask]>
Date:
Thu, 19 May 2016 11:22:02 -0400
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text/plain (136 lines)
Vlad, just curious, what chip size of C4? is it on BT substrate or  
polyimide?  thanks.
  jk
On May 19, 2016, at 11:04 AM, Vladimir wrote:

> Hi Gil,
>
> We investigated a case where C4!!! Has intermetallic up to 15  
> microns! But the joints didn't fai
>
> Regards,
>
> Vladimir
>
> Sent from my BlackBerry 10 smartphone on the Rogers network.
>   Original Message
> From: Zilber Gil
> Sent: Thursday, May 19, 2016 10:54
> To: [log in to unmask]
> Reply To: TechNet E-Mail Forum
> Subject: Re: [TN] Intermetallic and high temperature operation
>
> Hi David,
> Thank you for your prompt response. The paper I found is:
> app.aws.org/wj/supplement/WJ_1972_11_s536.pdf
> 1.
> So for the moment I can tell my boss that we can use the board at  
> 100 deg c for years, unless we will find more data that will warn us.
>
> Thank you and best regards,
>
> Gil
> From: David Hillman [mailto:[log in to unmask]]
> Sent: Thursday, May 19, 2016 4:12 PM
> To: TechNet E-Mail Forum; Zilber Gil
> Subject: Re: [TN] Intermetallic and high temperature operation
>
> Hi Gil - you hit on one of my soapbox topics so I have respond!  
> What data source are you citing that shows 6 micrometers of IMC  
> results in solder joint failure? And for the IMC, is it the Cu3Sn  
> or the Cu6SN5 phase? The industry is constantly "reminded" that  
> thick IMC is brittle and will cause a loss of solder joint  
> integrity but where is the data? Everyone is in consensus that IMC  
> phases have been shown to have brittle properties but when I push  
> for hard data/investigations/studies, demonstrating failures due to  
> excessive, thick IMC phase, the real root cause has always turned  
> out to be an out of control or excessive, abusive soldering process  
> - typically a soldering process most folks would say "ohh, I  
> wouldn't do that with my soldering process". For a dwell  
> temperature of 100C, I will grow approximately 5 micrometers of IMC  
> ( combine Cu3Sn and Cu6Sn5 phases) in 1660 hours using the standard  
> IMC equations for tin over copper (my calculations don't match the  
> details you listed). There are multiple examples of electronic  
> products in many different product use environments that easily  
> exceed that time and operate at that temperature yet we don't see  
> reports of product integrity data. Unless you have some nontypical  
> variable for your product in its use environment (basically, a  
> variation of Doug saying "it depends" but with less gray area), I  
> don't believe you have a solder joint integrity concern. Don't get  
> me wrong, I think its great that folks are looking at how much IMC  
> phase is produced/found on their solder joints but I think we  
> overstate the topic on most occasions.
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]<mailto:david.hillman@rockwellcollins 
> .com>
>
> On Thu, May 19, 2016 at 7:34 AM, Zilber Gil  
> <[log in to unmask]<mailto:[log in to unmask]>> wrote:
> Hello Technet`s,
>
> As we know above 6 micrometers of intermetallic (CuSn) could cause  
> failure due to brittle structure of the intermetallic. I found in  
> some experiment that at 100 deg C after 32 days the intermetallic  
> (CuSn from Sn-40Pb) grow in about 6 micron. Is it true? What should  
> I do if the board should see 100 deg C for long time and what about  
> >=90 dig?
>
> Thanks,
>
> Dr. Gil Zilber
> Technologiest
> Elta Systems Ltd.
>
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