Hi Chris - some more info to add to the good comments you have already
received. If you do a paper search, you will find that Craig Hamilton from
Celestica, and Dr. Chris Hunt, NPL, both did some very good work on copper
dissolution that you may find helpful. Jeff Kennedy, Ross Wilcoxon and I
published copper dissolution work for SAC305 and SN100C at the SMTA ICSR
conference (either 2012 or 2013) that we conducted as part of the NASA DoD
Lead-free Solder Project consortia work. Figure 12 has a copper thickness
versus wave solder processing time graph that might be useful. Good Luck.

Dave Hillman
Rockwell Collins
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On Mon, May 16, 2016 at 4:50 PM, Chris BALL <[log in to unmask]> wrote:

> Hello Gurus,
>
> Not sure who to ask or how best to ask it, but here goes:
>
> We've seen what appears to be a large % of the plating in hole barrel and
> board surface vanish during a wave solder operation. I can find some info
> about what is acceptable loss levels on component terminations but haven't
> found similar for the board itself.
>
> Need to find IPC references/recommendations for MAX copper leaching for
> solder source side of lands on the board and in hole barrels.
>
> Feeling old, tired, and thickheaded. Any help will be appreciated.
>
> Best Regards,
> Chris
> -------------------------------------------------
>    Chris Ball  (248)619-8430
>    Valeo - *G*roup *E*lectronics *E*xpertise and *D*evelopment *S*ervices
> (GEEDS)
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>
>
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