Hi Chris, 

There is a good paper by Trace Labs and Cisco that talks about dissolution of PCB Cu barrel plating with multiple thermal stresses 

https://www.nts.com/pdf/whitepapers/Dissolution-of-Printed-Circuit-Board-Copper-Barrel-Plating-Found-With-Multiple-Extended-Exposure-Thermal-Stress-Testing.pdf 

I don't think you are going to find an IPC references/recommendations for MAX copper leaching for 
solder source side of lands on the board and in hole barrels because the amount of copper leaching is dependent on the temperature, time, media and number of thermal exposures. It is my understanding that one of the reasons IPC uses 3x and 5x solder float exposures is to simulate a typical assembly process of two thermal soldering exposures and a repair (3x) or a severe assembly process where the PCB would be subjected to five thermal processes (5x). 

From my experience in Bell Labs and working for a Lucent Technolgies spins off we took a simplistic approach to specifying the minimum copper plating thickness in PCB PTHs. Rather that having multiple specifications for PCB based on the number of thermal processes they would be subjected to we had one specification for PCB PTH copper thickness to meet the worst case of 5x thermal processes. I don't have an electronic copy of the specification but it basically required the copper plating thickness in a PCB PTH to be greater than or equal to 1 mil minimum. We also relaxed the minimum copper plating thickness to be greater than or equal to 0.8 mils for small diameter PCB PTHs (i.e., PTHs drilled at 10.5 mil diameter or less). 

Since you indicated you are seeing a large % of plating in hole barrels and board surfaces vanishing during wave soldering that means you have must have done cross sections to show the large %. My suggestion would to send Steve Zeva photomicrographs of a PTH before and after wave soldering and have TN people comment on the amount of original copper plating and the amount that is dissolved. That way you may get some idea if the problem is the original plating thickness is too thin or if your thermal process is too aggressive. 




Regards, 

George 

George M. Wenger 
Failure Signature & Characterization Lab LLC 
609 Cokesbury Road, High Bridge, NJ 08829 
(908) 638-8771 (Home) (732)-309-8964 (Cell) 
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----- Original Message -----

From: "Chris BALL" <[log in to unmask]> 
To: [log in to unmask] 
Sent: Monday, May 16, 2016 5:50:55 PM 
Subject: [TN] what is acceptable % of copper leaching in barrel and pad 

Hello Gurus, 

Not sure who to ask or how best to ask it, but here goes: 

We've seen what appears to be a large % of the plating in hole barrel and 
board surface vanish during a wave solder operation. I can find some info 
about what is acceptable loss levels on component terminations but haven't 
found similar for the board itself. 

Need to find IPC references/recommendations for MAX copper leaching for 
solder source side of lands on the board and in hole barrels. 

Feeling old, tired, and thickheaded. Any help will be appreciated. 

Best Regards, 
Chris 
------------------------------------------------- 
Chris Ball (248)619-8430 
Valeo - *G*roup *E*lectronics *E*xpertise and *D*evelopment *S*ervices 
(GEEDS) 
150 Stephenson Highway 
Troy,MI 48083 


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