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April 2016

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Subject:
From:
"MacFadden, Todd" <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, MacFadden, Todd
Date:
Fri, 8 Apr 2016 17:12:34 +0000
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Dave is correct about min dielectric thickness. Per UL requirements, you should have minimum adjacent layer spacing of 0.4mm between the +12V and -12V lines. If it is not possible to achieve min 0.4mm space, then at least 3 plies of prepreg are required between them. 

Todd 



-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David Hillman
Sent: Friday, April 8, 2016 12:53 PM
To: [log in to unmask]
Subject: Re: [TN] Recommendations for Failure Analysis / Root Cause of PCBA Failure...

Hi Steve - we need the Technet board subject matter experts help on this but having that much electrical potential would certainly make for having possible corrosion issues and failure modes (such as CAF) if the board fabrication was not done correctly. There also could be a design rule violation such as that dielectric layer being too thin  - ok TechNet board folks - thoughts?

Dave

On Fri, Apr 8, 2016 at 11:44 AM, Steve Gregory <[log in to unmask]> wrote:

> Hi again Dave,
>
> So the PCB is a .090" thick, 8-layer board, the stack-up is this:
>
> Soldermask
> Layer 1
> ----------
> Ground
> ----------Pre-preg
> Layer 3
> ----------
> +12V
> ----------Pre-preg
> -12V
> ----------
> Layer 6
> ----------Pre-preg
> Ground
> ----------
> Layer 8
> Soldermask
>
> Steve
>
>
> On Fri, Apr 8, 2016 at 10:18 AM, David Hillman < 
> [log in to unmask]> wrote:
>
>> Hi Steve - yes, you have enough physical details that a lab that 
>> routinely conducts FA work on electronic assemblies (there are 
>> several who are part of Technet) would have a reasonable chance of 
>> finding the root cause. At a very minimum with the details you have 
>> on this issue, the laboratory should be able to rule out possible 
>> root causes even if they can't find a specific root cause. I didn't 
>> see any dendritic shorting - is the belief that the shorting is internal to the pwb?
>>
>> Dave Hillman
>> Rockwell Collins
>> [log in to unmask]
>>
>>
>> On Fri, Apr 8, 2016 at 11:00 AM, Steve Gregory <[log in to unmask]>
>> wrote:
>>
>>> Good Morning All,
>>>
>>> We have an assembly that we build here for a customer that we built 
>>> for some time, over 2,000 assemblies. There have been some failures 
>>> that our customer has had field returns with that are beginning to 
>>> escalate. There have been 12 field failures that we know of. The 
>>> failures are avionic assemblies that have been in the field ranging from 111 days to 472 days.
>>> The actual failures are internal +12V to -12V shorts and we need to 
>>> know why. I have two failed assemblies here. Here are a couple of 
>>> external photos of a via that shows the short:
>>>
>>> http://stevezeva.homestead.com/Internal_Short.jpg
>>>
>>> http://stevezeva.homestead.com/Internal_Short_Close.jpg
>>>
>>> So my question is, can a lab take these boards and examine them to 
>>> determine what the root cause actually is from the two assemblies 
>>> that I have, or does there need to be more samples? What is the 
>>> range we should expect to pay for this type of analysis?
>>>
>>> We're trying to work with our PCB vendor on this issue, but I have 
>>> also been asked by my boss to pursue this with a third party.
>>>
>>> Thanks!
>>>
>>> Steve
>>>
>>>
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>>
>
>
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