(1) solder mask initiated cracking observed before - the small  
opening or mis alignment  might be the contributing factor. In  
addition, if you go down to -55 C, you mask is pretty hard at that  
temperature - assume no ice or condensation take place and TC done   
properly.
(2) large chip and low Tg stuff normally got trouble unless you  
layout done properly (Cu balance, not much warpage upon TC).
(3) solder ball pattern and size also contribute to the reliability  
and of course, the location of the device on the assembly.  Center  
rows - avoid edge usually are good but made inspection almost  
impossible (visual or X-ray... you can't see fine crack in X-ray  
anyhow, unless you do thermal shock and check with resistance change  
using daisy chain at developing stage).
(4) add to the movement (press) appear to be one of the design  
element, direction and tolerance of the move require carefully  
analysis.  WLCSP does no like to be twist and bent or knock on it,  
unless you protected somewhat.
Best way to test it new device, new application and new thin PCB, get  
the dummy daisy chain device and populated with other stuff, do  
thermal shock/drop/press (using robot may be for 10,000 to 50,000)  
simulation and check for resistance change or open/short.  (yes,  
short, sometime, the two balls mushed together).  you got your answer  
quickly, rather than everybody's best guesstimate.  my 1.4 cents.
         jk
On Apr 20, 2016, at 1:56 PM, Mattix, Dwight wrote:

> For one thing, distance from neutral pt of the flipchip to furthest  
> out ball tend to be shorter than on a packaged part.  Someone  
> should have kept me from dozing off during those physics and  
> statics/dynamics lectures. My son (M.E. student) just completed  
> them with far better performance than I – maybe I should consult  
> him. ;)
>
> I wonder if it’s related to the seeming randomness of flipchip ball/ 
> bump patterns.
>
> From: David Hillman [mailto:[log in to unmask]]
> Sent: Wednesday, April 20, 2016 9:27 AM
> To: TechNet E-Mail Forum <[log in to unmask]>; Mattix, Dwight  
> <[log in to unmask]>
> Subject: Re: [TN] .031 PCB and WLCSP
>
> Hi Dwight - your experience has been my experience but our latest  
> testing is beginning to show we may want to challenge the NSMD  
> convention for components that are 0.3mm or smaller. There may be a  
> solder volume/component size/CTE relationship for thermal cycle  
> conditions where the smaller technologies are not as influenced as  
> our knowledge of 0.4mm or larger. Lots more testing to do but I am  
> starting to think we might have a rule of thumb for smaller versus  
> larger on SMD and NSMD configurations.
>
> Dave
>
> On Wed, Apr 20, 2016 at 10:45 AM, Mattix, Dwight  
> <[log in to unmask]<mailto:[log in to unmask]>> wrote:
> Interesting.  That's 180 out from my .4, .35mm and .3mm experience  
> on larger packages.  That included drop and Izod impacts as well  
> done to a Jedec package qual standard.
>
> What size package and pin count?  Being flip chip I'd imagine  
> pretty low pin count and not necessarily a symmetrical placement of  
> balls like in a full array BGA?
>
>
> -----Original Message-----
> From: MacFadden, Todd  
> [mailto:[log in to unmask]<mailto:[log in to unmask]>]
> Sent: Wednesday, April 20, 2016 8:12 AM
> To: Mattix, Dwight  
> <[log in to unmask]<mailto:[log in to unmask]>>;  
> TechNet E-Mail Forum <[log in to unmask]<mailto:[log in to unmask]>>
> Subject: RE: [TN] .031 PCB and WLCSP
>
> Hi Dwight,
>
> That is what we thought as well, but for 0.4mm pitch flip chips, we  
> get better solder joint reliability with solder mask defined pads  
> than with Cu-defined pads. Our hypothesis is that the greater  
> standoff height and more consistent solder joint shape associated  
> with SM-defined configuration outweighs the benefit of the  
> increased bond area, but inconsistent solder joint shape with Cu- 
> defined configuration.
>
> Granted, this improvement was noted for temp cycling. I can't speak  
> to drop. I really think Curt is going to need some sort of staking  
> or underfill for that remote control application.
>
> Todd
>
>
> -----Original Message-----
> From: Mattix, Dwight  
> [mailto:[log in to unmask]<mailto:[log in to unmask]>]
> Sent: Wednesday, April 20, 2016 10:17 AM
> To: TechNet E-Mail Forum; MacFadden, Todd
> Subject: RE: [TN] .031 PCB and WLCSP
>
> S/M define pads on a ball and no underfill or corner staking?    
> Standby for cracked solder joints.
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]<mailto:[log in to unmask]>] On  
> Behalf Of MacFadden, Todd
> Sent: Wednesday, April 20, 2016 5:10 AM
> To: [log in to unmask]<mailto:[log in to unmask]>
> Subject: Re: [TN] .031 PCB and WLCSP
>
> Without underfill in this application your greatest challenge for  
> solder joint reliability will likely be from drop rather than  
> cyclic strain and fatigue. It's a small device (9x9mm) so that risk  
> may be relatively low, but here are some things you may consider:
>
> * PCB-side solder joint area should match the device side pad size  
> area (i.e., UBM). The UBM diameter will be smaller than the 0.2mm  
> ball diameter (you may need to ask the device supplier for this  
> info since it's not usually provided on the datasheet).
>
> * Use solder mask defined pads because: (1) a Cu-defined PCB pad  
> <0.2mm is not possible by most PCB fabricators if there are uvias  
> in the pads; (2) solder area of the PCB pads should be of  
> consistent size; this is not possible with Cu-defined pads due to  
> exit traces, which draw solder away and distort the shape of solder  
> joints inconsistently. Solder mask defined also allows for larger  
> Cu pad, for which the PCB fabricator will thank you.
>
> * Is corner staking an option? In the absence of full underfill,  
> your best bet to pass drop test may be to apply epoxy dots or lines  
> on the corners.
>
> Good luck!
> Todd
>
>
> -------------------------------------------------------
> Todd MacFadden
> Component Reliability Engineering
> Bose Corporation
> 1 New York Ave, MS 415
> Framingham, MA 01701
> 508.766.6259
> -------------------------------------------------------
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]<mailto:[log in to unmask]>] On  
> Behalf Of Curt McNamara
> Sent: Tuesday, April 19, 2016 6:56 PM
> To: [log in to unmask]<mailto:[log in to unmask]>
> Subject: [TN] .031 PCB and WLCSP
>
> I am reviewing a design with a .4 mm pitch, .2 mm ball WLCSP (9x9)  
> on a 4 layer .031 FR4 pcb.
>
> These will be used like a remote control, so there will be force  
> applied, however there are supports for the PCB.
>
> Due to the presence of switches with cleaning restrictions,  
> underfill is not possible.
>
> Looking for any comments on potential reliability concerns. The  
> design could be changed to .064 if that would help.
>
> Thanks in advance!
>
>     Curt
>
>
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