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March 2016

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DesignerCouncil <[log in to unmask]>
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Designers Council Forum <[log in to unmask]>, Jack Olson <[log in to unmask]>
Date:
Wed, 16 Mar 2016 21:10:44 +0000
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"(Designers Council Forum)" <[log in to unmask]>, "Anderson, Veronika" <[log in to unmask]>
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"Anderson, Veronika" <[log in to unmask]>
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The percentage of hole fill with solder depends on Class (1,2,3) of the final product.
Refer to IPC-J-STD-001, Paragraph 6.2.2 and Table 6-4.
Based on your number 75% I assume that you are building Class 3 product and your vendor does not have AOI equipment.
Therefore, they cannot verify the percentage of fill. That is why they want to have the solder to be visible from the other side.

You will find the Thermal Relief spoke calculations in IPC -2222, 9.1.2. However, as stated at the end of the paragraph, "calculated spoke width shall not violate current carrying capacity requirements". Personally, I never fill comfortable with the calculated number for high current traces. I always increase it.      
I recommend to use Saturn PCB Toolkit (free from Saturn PCB Design, Inc.) and increase the number based on the copper thickness, current and your gut's feelings. 
 
Regards, 

Veronika Anderson C.I.D | Sr. Electrical/Mechanical Design Engineer | Excelitas Technologies

My old phone number +1 626.967.9521 x 236 no longer works.

Office:  +1 626-593-6025.
1330 East Cypress Street, Covina, CA 91724 USA 
[log in to unmask]
www.excelitas.com

-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Wednesday, March 16, 2016 12:30 PM
To: [log in to unmask]
Subject: [DC] Hole Fill and Thermal Relief

I posted this to IPC TechNet, but I think many people are busy at APEX this
week:

-=-=-=-

Maybe I should know better than to ask two questions in the same email, but they're related...
I got into a discussion about the hole fill requirement for some large through-hole power devices and connectors. The supplier is worried about using a "percentage" hole fill measurement, because he says that even if the hole is 75% full (or whatever percentage we want to use) the hole wall will not be WETTED 75%. He maintains that the cold solder can extend up farther than the actual portion that makes a good joint. So he is looking at the TOP PAD WETTING for verification of a good solder joint, even though we don't require it.

Q1) It seems like an inspection procedure looking for WETTING instead of HOLE FILL is not what is intended in IPC, but does he have a point? The hole fill problem is with Selective Soldering, not Reflow

Q2) Wanting to provide bare board designs using good DFM practices, I would be willing to reduce my thermal spoke widths so the solder will flow better, but I can't find a calculation that would tell me what I need for something like 10A. There is nothing about this in the IPC-2152 Current Carrying standard. Is there a rough guideline I can use for current through planes using thermal relief??

thanks,
Jack


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