I have a design rule calculator that I created a while back that calculates a bunch of manufacturability rules.  I had to go back and re-learn what I used for this calculation. 

(PCB Thickness / 2)  -  (minimum V-score retention thickness /) * 0.6     [This is the designed maximum material removal]

+ v-score tolerance  [a pre-determined value based on known fabricator's capabilities, variable based on which fabricator level is used for this board]

+ (feature location DTP /  2)   [ for copper accuracy]

+ minimum copper spacing  [an added "fudge factor" that is relative to design intent and fabricator's capabilities and etch factor requirements]

This generally solves to 26 mils, or 28 for lower level vendors.  This is the worst case for v-score angle, it can be adjusted for inner layers by changing the board thickness variable to match the location of the desired plane.  For routed edges, set board thickness = minimum v-score retention (creates 0 v score angle).  

As for power plane pullback - if you have room, I suppose it can't hurt.  But it's likely not helping, either.  Anything more than 2H or 3H is not going to be effective for EMI sensitive frequencies.  If you have EMI currents on the power plane, you likely have an unshielded trace or a copper slot somewhere that makes a much more effective antenna than the plane edges.

Thanks, William, for giving me a reason to go back and review this.

Pete

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