Hi Bill,
*Personally: *
I always use at least 20, prefer 30, and if it's a large board with plenty
of space, I go 50.
*Fabrication:*
I've heard if you get near 11, they get nervous and you might get a phone
call (overheard in IPC discussions). I've also heard that some designers
want to go all the way to the edge, so they let the fabricator "trim back"
the minimum amount they need to settle their nerves, but in my opinion,
this is a cheesy design practice and I wouldn't recommend it.
*The Problem:*
If designers reduce the distance from the board edge to the nearest
conductive features, it creates a hazard for the fabricator, because
several of the acceptance criteria are based on a percentage of that
distance. For example, if the router makes "nicks" in the edge, they are
acceptable as long as they don't extend 50% of the distance to conductive
features. The more you reduce that distance, the more risk of creating a
rejectable product, or at least an inspection/approval headache. So, the
committee is proposing a change to the wording of the IPC-6012
acceptability document to be:
3.3.1 Edges When edge spacing is designed in accordance with IPC-2222,
nicks or crazing along the edge of the printed board, edge of cutouts and
edges of non-plated holes are acceptable provided the penetration does not
exceed 50% of the distance from the edge to the nearest conductor or 2.5 mm
[0.0984 in], whichever is less.
When edge spacing is designed in accordance with IPC-2222, the distance
between the haloing penetration and the nearest conductive feature shall
not be less than the minimum lateral conductor spacing, or 100 μm [3,937
μin] if not
specified.
When edge spacing is not designed in accordance with IPC-2222, evaluations
for nicks, crazing and haloing shall be AABUS.
onward thru the fog,
Jack
On Wed, Jan 6, 2016 at 3:00 PM, Brooks, William <
[log in to unmask]> wrote:
> Why "surprising" Frank? I like to generate discussion... I like to see
> what others are doing... I'm not lost or looking for guidance, per se. I'm
> soliciting opinions, reasons and practical usage by other designers like
> me...
>
> From a strictly manufacturing point of view you should always have some
> pull back on internal copper plane layers.
> Meaning... the internal copper planes should not extend all the way to the
> routed edges of the board.
> Why? Because the board material needs it to bond at the edges during
> lamination and also to provide a seal at the edges from moisture
> incursion...
> and you really don't want a copper burr along the edge of the board that
> could short to anything that touches the edge if the copper plane gets
> exposed.
>
> The question is how much pull back do you think is enough for a typical
> multilayer FR4 board?
> Some cad tools have a default setting... Altium defaults to 20 mils.
> What's your common practice? What do the glass/epoxy board manufacturers
> prefer?
>
>
> William Brooks, CID+
> Printed Circuit Designer
> 2747 Loker Ave West
> Carlsbad, CA 92010-6603
> 760-930-7212
> Fax: 760.918.8332
> Mobile: 760.216.0170
> E-mail: [log in to unmask]
>
>
>
>
> -----Original Message-----
> From: Frank Kimmey [mailto:[log in to unmask]]
> Sent: Wednesday, January 06, 2016 12:37 PM
> To: (Designers Council Forum); Brooks, William
> Subject: Re: [DC] pull back clearance on internal planes
>
> William,
> This is a bit surprising from you but, it all depends on what you are
> targeting.
> If you want to make life easier for you fabricating then you will need a
> minimum of whatever your positional tolerance for routing are.
> If you are looking to minimizing your risk for leakage (i.e. High Speed,
> RF, etc.) you will need to add to the clearances. I stopped pulling back
> planes and just accepted the minor cost hit (quicker on the design time and
> not enough signal issues to warrant the added time to create keep outs).
> In the more sensitive stuff, I like to keep 50 mils back and add ground
> guards when there is enough room.
> So I guess this another of the it depends kinda answers, what are the
> criteria you need to meet and what trade-offs are acceptable.
> I don't think there are real minimum requirements, but there may be good
> practices to follow for you specific needs.
> Good luck,
> FNK
>
> Frank Kimmey CID+
>
>
> Sent from my iPad
>
> > On Jan 6, 2016, at 12:02 PM, Brooks, William <
> [log in to unmask]> wrote:
> >
> > What do you recommend for clearance from the edge of an internal plane
> to the board edge?
> >
> >
> >
> > William Brooks, CID+
> > Printed Circuit Designer
> > 2747 Loker Ave West
> > Carlsbad, CA 92010-6603
> > 760-930-7212
> > Fax: 760.918.8332
> > Mobile: 760.216.0170
> > E-mail: [log in to unmask]
> >
> >
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