Adam, 20H does not attenuate or stop noise between planes, think of it as leading noise out the edge of the plane. Once an unwanted signal is created it is going to go somewhere, is the unwanted signal more detrimental inside or outside the board?, in the neighbor circuit?
When using vias to create an electrical barrier at the board edge or between circuits one row of vias has limited effect. Two or three rows of vias may be more effective than reducing via center to center distance.
Like most "rules" in PCB design these have many caveats. Unfortunately for us the R+D effort to accurately answer the caveat requirements is prohibitive for even a modest sized board. This leaves us with rules of thumb and "it worked in the past", where I would put the 20h rule, a piece of the puzzle. Something in there may explain why two intelligent people come up with opposing results.
Dave
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Adam Domoe
Sent: Thursday, January 07, 2016 9:41 AM
To: [log in to unmask]
Subject: Re: [DC] pull back clearance on internal planes
I stick with 25 mils unless it's a thick board with V-scores - then I follow instruction from the board house.
We have some designs that get within 5 mils on outer layers. This is mostly a carry-over from legacy boards that I will typically change on revision unless it's not allowed (usually due to concerns about the need to re-qualify).
I have a question for those of you who pull back the power planes: are you also adding shielding vias around the edge of the board?
This reminded me of an old rule of thumb called the 20H rule where designers would pull back power planes 20X the distance between it and the nearest GND plane. The 1st link below is to a paper that showed the application of this rule actually increases radiation for 2 plane structures and has no significant impact on 3 plane structures. The 2nd link is to a paper that seems to dispute the methodology used in the first paper and shows the 20H rule is effective in reducing radiation. To be honest the majority of what is presented in the papers is over my head; I pretty much just read the intro and the conclusion. Anyone have an idea who is right? My guess is it's a big "it depends".
On new designs if space permits it I put a GND (or chassis GND) ring around the edge of the board on each layer and stitch with vias spaced at no greater than 1/8th wavelength of the highest frequency on the board (usually aim for 1/20th).
Links (can also be found quickly by googling "20H rule"):
http://www.sigrity.com/papers/epep2000/epep_20h.pdf
http://www.google.com/url?sa=t&rct=j&q=&esrc=s&frm=1&source=web&cd=4&cad=rja&uact=8&ved=0ahUKEwje0fXa4pfKAhUDeD4KHdJqBbkQFggzMAM&url=http%3A%2F%2Fpiers.org%2Fpiersonline%2Fdownload.php%3Ffile%3DMDYwOTA2MDAxNjQzfFZvbDNObzdQYWdlMTA5N3RvMTEwMS5wZGY%3D&usg=AFQjCNHke1JPkVD_TePQMe7xZGjO_uuZ2w
Adam Domoe
L-3 Communications
Cincinnati Electronics
7500 Innovation Way
Mason, OH 45040
(513)573-6928 (office)
(513)573-6100 (main)
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Brooks, William
Sent: Wednesday, January 06, 2016 3:03 PM
To: [log in to unmask]
Subject: [DC] pull back clearance on internal planes
What do you recommend for clearance from the edge of an internal plane to the board edge?
William Brooks, CID+
Printed Circuit Designer
2747 Loker Ave West
Carlsbad, CA 92010-6603
760-930-7212
Fax: 760.918.8332
Mobile: 760.216.0170
E-mail: [log in to unmask]
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