So in the case of conformal coat, this is applied over top the residue? Does this lead to latent issues?
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Ed Popielarski
Sent: Thursday, November 05, 2015 12:35 PM
To: [log in to unmask]
Subject: Re: [TN] Pierced Terminal
I agree 100%. "No clean" flux really should be called "Don't clean"! The bad guys (ionics) don't necessarily "go away", they are well encapsulated in the residue. Disturbing the residue is opening Pandora's box.
Ed Popielarski
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-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory
Sent: Monday, November 02, 2015 8:34 AM
To: [log in to unmask]
Subject: Re: [TN] Pierced Terminal
Hi Chris,
Sorry I was out on Friday, so I apologize for the late response. I have your pictures posted, they are here:
http://stevezeva.homestead.com/Chris_Flux_Residue.jpg
As Guy said, I would leave it alone. I agree that an attempt to clean this you would run the risk of wicking things up into the insulation. IMHO, it looks fine to me.
Steve
On Thu, Oct 29, 2015 at 5:43 PM, Thierolf, Chris @ MPSG - SPD < [log in to unmask]> wrote:
> I'm seeking some input to a solder condition that gets scrutinized in
> many directions. For the soldering of a stranded 10-12awg stranded
> wire to a pierced resistor terminal, a no clean L0 or L1 (RO/RE) flux
> is used with
> 63/37 solder. This is a single solder joint on a panel mount resistor,
> so no PCB involved. Flux residue is observed and assembly rejected by
> QC but manufacturer claims its no worry, and no clean flux. My
> observation says it presents no electrical or operational issue, not a
> violation of J-STD-001, but perhaps a visual issue per IPC-A-610, sec
> 10.6.4 "Flux residue inhibits visual inspection" if floor inspector
> claims he cannot see the solder joint clearly, which has occurred. We
> can state "clean the solder joint" (relatively speaking), but what
> really is clean in this case? Should we be forced to inspect these
> joints with 4x mag, as some are doing, or generate a simple guideline
> that allows residue up to a certain level? What is this level?
>
> I have a picture of a failed solder joint if interested, but not sure
> where to upload.
>
>
> ______________________________________
> [Disc3.png]
> Chris Thierolf
> Principal EE and Project Engineer
> L-3 Electronic Systems Segment
> SPD Electrical Systems
> 13500 Roosevelt Boulevard
> Philadelphia, PA 19116
> Phone: (215) 698-6390 Fax: (215) 677-4736
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