Yes, have a lot of experience with this. It's a short list of fabs that can build a (Pb-free solder) survive-able and reliable pwb with 3 layers uVia on core via. Doubt the honesty or experience of any who say they do 4n4 over multilayer core via reliably.  4n4 works just fine -- until it doesn't and it won't give you a heads up before that time it completely blows up in SMT reflow.

At 3n3 the list of capable fabs gets real short, real fast as you go above 1mm overall thick and toward 2.0mm overall thick. By the time you get to 3n3 at 2.0mm overall thick I can count on less than 2 hands the number of fabs I've been able to qual thru IST  (9x @260C precondiction and to 1000 cycles to 150C).

Lots of bake time at each lamination sub, top quality copper in the via, nothing less than San-Ei type via fill and a tough laminate to start with (e.g. 370HR, Hitachi 679G level of mechanical performance).


I can point out one supplier facility who has completed that particular IST protocol up to 30 layers of 3n3 with uVia on core via successfully with several sizeable successful pwb designs.

I realize that the plural of anecdote is still not data so YMMV,
dw

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Wayne Thayer
Sent: Monday, November 30, 2015 4:27 PM
To: [log in to unmask]
Subject: Re: [TN] Stacked Via Reliability Risk?

Hi Todd-

Most of the really high density PCB fabricators won't do this. I use "really high" as opposed to "HDI" because HDI was supposed to mean "chips first" techniques and was originally developed at GE.

Besides the reason you've stated below, I've gotten:

-Cap ends up too thin to stop the laser on -Surface the laser is shooting towards is too unpredictable in terms of flatness or heat sinking capability

Wayne Thayer
________________________________________
From: TechNet [[log in to unmask]] on behalf of MacFadden, Todd [[log in to unmask]]
Sent: Monday, November 30, 2015 8:47 AM
To: [log in to unmask]
Subject: [TN] Stacked Via Reliability Risk?

I have heard that stacking microvias on resin-filled buried vias can pose a reliability risk due to resin expansion at high temperatures, which can cause the copper cap to lift off the buried via, potentially causing an open. Here is one source that describes this risk:


http://pcb.iconnect007.media/index.php/article/66028/reid-on-reliability-lifted-pad-stacked-microvia-failure/66031/?skin=pcb


Nevertheless, this type of construction is plainly sanctioned in IPC-2226 (HDI Type III), so I wonder how serious this risk is, and/or if this is something the IPC-2226 Committee (D-41?) is planning to address.

Does anyone have any experience with or knowledge of this risk? How serious is the risk? Do you have internal rules/guidelines specifically to avoid this structure? (I'm referring only to stacked vias atop resin-filled buried vias; my understanding is that stacked, Cu-filled uvias are not a reliability risk. Correct assumption?)



Thanks in advance,
Todd MacFadden

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