Yes, this can happen, but is actually very rare. The bond between the
stacked and buried microvias is actually stronger than having a single
unfilled via going all the way through the PWB with multi-layer copper
traces connected to it (that is one of the reasons for the stacked microvia
design). This is because in the stacked microvia configuration, the entire
"stack" is more solidly bound than individual traces emanating out in every
direction from the exterior via wall.
If you think of a standard via as being a rivet, any expansion of the PWB
in the Z-axis will apply stress to the innerlayer trace connections to the
vias, thus shearing them off. When the board cools, the sheared traces can
re-connect with their stubs on the exterior via wall, causing an
intermittent open that can pass all testing. The same thing can in the
copper cap configuration, the cap can lift off of the buried via due to
thermal expansion in the Z-axis, but is less likely to do so because of the
resin backfilling usually associated with this design. You are correct in
assuming that the stacked, Cu-filled uvias are much less of a reliability
risk, however I would not choose them over the stacked and filled microvias
just for that reason, except for if the PWB is going to see relatively high
processing or operating temperatures. The copper filled vias are a much
better choice in that case. But the most important thing to keep in mind is
the material choice and the fabrication method used; if the PWBs are
properly baked out prior to processing, and the PWB is not going to be
operating at high thermal cycles, then the stacked microvia configuration is
quite reliable.
Both the separated buried via stacks and the sheared traces from the via
wall are caused by the same issue; thermal expansion in the Z-axis due to
heating of entrapped moisture (steam) inside the PWB during processing, or
sometimes during operation, although this second cause is very rare.
Refer to the material properties of the PWB within the slash sheets of IPC
4101, as there is some good information on the stacked microvia design in
there as well.
But most importantly, pay attention to the instructions within IPC 1601 to
ensure the board is properly baked prior to processing.
dean
-----Original Message-----
From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of
MacFadden, Todd
Sent: Monday, November 30, 2015 7:47 AM
To: [log in to unmask]
Subject: [DC] Stacked Via Reliability Risk?
I have heard that stacking microvias on resin-filled buried vias can pose a
reliability risk due to resin expansion at high temperatures, which can
cause the copper cap to lift off the buried via, potentially causing an
open. Here is one source that describes this risk:
http://pcb.iconnect007.media/index.php/article/66028/reid-on-reliability-lif
ted-pad-stacked-microvia-failure/66031/?skin=pcb
Nevertheless, this type of construction is plainly sanctioned in IPC-2226
(HDI Type III), so I wonder how serious this risk is, and/or if this is
something the IPC-2226 Committee (D-41?) is planning to address.
Does anyone have any experience with or knowledge of this risk? How serious
is the risk? Do you have internal rules/guidelines specifically to avoid
this structure? (I'm referring only to stacked vias atop resin-filled buried
vias; my understanding is that stacked, Cu-filled uvias are not a
reliability risk. Correct assumption?)
Thanks in advance,
Todd MacFadden
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