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October 2015

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Subject:
From:
Guy Ramsey <[log in to unmask]>
Reply To:
TechNet E-Mail Forum <[log in to unmask]>, Guy Ramsey <[log in to unmask]>
Date:
Fri, 30 Oct 2015 08:36:44 -0400
Content-Type:
text/plain
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text/plain (76 lines)
Cleanliness levels for rework are the same as for production. 
Attempting to remove no-clean flux residue can be very risky, much worse
than leaving it alone. 

-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Thierolf, Chris @ MPSG -
SPD
Sent: Thursday, October 29, 2015 7:44 PM
To: [log in to unmask]
Subject: [TN] Pierced Terminal

I'm seeking some input to a solder condition that gets scrutinized in many
directions. For the soldering of a stranded 10-12awg stranded wire to a
pierced resistor terminal, a no clean L0 or L1 (RO/RE) flux is used with
63/37 solder. This is a single solder joint on a panel mount resistor, so no
PCB involved. Flux residue is observed and assembly rejected by QC but
manufacturer claims its no worry, and no clean flux. My observation says it
presents no electrical or operational issue, not a violation of J-STD-001,
but perhaps a visual issue per IPC-A-610, sec 10.6.4 "Flux residue inhibits
visual inspection" if floor inspector claims he cannot see the solder joint
clearly, which has occurred. We can state "clean the solder joint"
(relatively speaking), but what really is clean in this case? Should we be
forced to inspect these joints with 4x mag, as some are doing, or generate a
simple guideline that allows residue up to a certain level? What is this
level?

I have a picture of a failed solder joint if interested, but not sure where
to upload.


______________________________________
[Disc3.png]
Chris Thierolf
Principal EE and Project Engineer
L-3 Electronic Systems Segment
SPD Electrical Systems
13500 Roosevelt Boulevard
Philadelphia, PA 19116
Phone: (215) 698-6390    Fax: (215) 677-4736


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